Commit 1fa7bb12 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Program MSA timing delay on ilk/snb/ivb 



Grab the DRRS MSA timing delay value from the VBT
and program things accordingly. Only ilk/snb/ivb have
this so presumably on hsw+ we don't need it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220310004802.16310-6-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent b395c29a

drivers/gpu/drm/i915/display/intel_display.c

+6 −2
Original line number Diff line number Diff line
@@ -3596,6 +3596,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 
	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);



	val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);

	val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);



	intel_de_write(dev_priv, PIPECONF(pipe), val);

	intel_de_posting_read(dev_priv, PIPECONF(pipe));
@@ -3884,6 +3885,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, 


	pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;



	pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);



	pipe_config->csc_mode = intel_de_read(dev_priv,

					      PIPE_CSC_MODE(crtc->pipe));
@@ -5364,8 +5367,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, 
				      &pipe_config->dp_m2_n2);

	}



	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d\n",

		    pipe_config->framestart_delay);

	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",

		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);



	drm_dbg_kms(&dev_priv->drm,

		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
@@ -6264,6 +6267,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_X(output_types);



	PIPE_CONF_CHECK_I(framestart_delay);

	PIPE_CONF_CHECK_I(msa_timing_delay);



	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);

	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −0
Original line number Diff line number Diff line
@@ -1155,6 +1155,7 @@ struct intel_crtc_state { 
	u8 update_planes;



	u8 framestart_delay; /* 1-4 */

	u8 msa_timing_delay; /* 0-3 */



	struct {

		u32 enable;

drivers/gpu/drm/i915/display/intel_drrs.c

+3 −0
Original line number Diff line number Diff line
@@ -83,6 +83,9 @@ intel_drrs_compute_config(struct intel_dp *intel_dp, 
		return;

	}



	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))

		pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;



	pipe_config->has_drrs = true;



	pixel_clock = connector->panel.downclock_mode->clock;

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -3702,6 +3702,8 @@ 
#define   PIPECONF_INTERLACE_IF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */

#define   PIPECONF_INTERLACE_PF_ID_DBL_ILK	REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */

#define   PIPECONF_EDP_RR_MODE_SWITCH		REG_BIT(20)

#define   PIPECONF_MSA_TIMING_DELAY_MASK	REG_GENMASK(19, 18) /* ilk/snb/ivb */

#define   PIPECONF_MSA_TIMING_DELAY(x)		REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))

#define   PIPECONF_CXSR_DOWNCLOCK		REG_BIT(16)

#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	REG_BIT(14)

#define   PIPECONF_COLOR_RANGE_SELECT		REG_BIT(13)