Commit 2060a689 authored by Mika Kahola's avatar Mika Kahola Committed by Stanislav Lisovskiy
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drm/i915/display/dg2: Set CD clock squashing registers 



Set CD clock squashing registers based on selected CD clock.

v2: use slk_cdclk_decimal() to compute decimal values instead of a
    specific table (Ville)
    Set waveform based on CD clock table (Ville)
    Drop unnecessary local variable (Ville)
v3: Correct function naming (Ville)
    Correct if-else structure (Ville)
[v4: vsyrjala: Fix spaces vs. tabs]
[v5: vsyrjala: Fix cd2x divider calculation (Uma),
               Add warn to waveform lookup (Uma),
               Handle bypass freq in waveform lookup,
               Generalize waveform handling in bxt_set_cdclk()]

Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-4-mika.kahola@intel.com
parent ba884a41

drivers/gpu/drm/i915/display/intel_cdclk.c

+40 −1
Original line number Diff line number Diff line
@@ -1638,6 +1638,26 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 
	}

}



static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,

				 int cdclk)

{

	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;

	int i;



	if (cdclk == dev_priv->cdclk.hw.bypass)

		return 0;



	for (i = 0; table[i].refclk; i++)

		if (table[i].refclk == dev_priv->cdclk.hw.ref &&

		    table[i].cdclk == cdclk)

			return table[i].waveform;



	drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",

		 cdclk, dev_priv->cdclk.hw.ref);



	return 0xffff;

}



static void bxt_set_cdclk(struct drm_i915_private *dev_priv,

			  const struct intel_cdclk_config *cdclk_config,

			  enum pipe pipe)
@@ -1645,6 +1665,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	int cdclk = cdclk_config->cdclk;

	int vco = cdclk_config->vco;

	u32 val;

	u16 waveform;

	int clock;

	int ret;



	/* Inform power controller of upcoming frequency change. */
@@ -1688,7 +1710,24 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
			bxt_de_pll_enable(dev_priv, vco);

	}



	val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) |

	waveform = cdclk_squash_waveform(dev_priv, cdclk);



	if (waveform)

		clock = vco / 2;

	else

		clock = cdclk;



	if (has_cdclk_squasher(dev_priv)) {

		u32 squash_ctl = 0;



		if (waveform)

			squash_ctl = CDCLK_SQUASH_ENABLE |

				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;



		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);

	}



	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |

		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |

		skl_cdclk_decimal(cdclk);

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -10543,6 +10543,14 @@ enum skl_power_gate { 
#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)

#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)









/* CDCLK_SQUASH_CTL */









#define CDCLK_SQUASH_CTL		_MMIO(0x46008)









#define  CDCLK_SQUASH_ENABLE		REG_BIT(31)









#define  CDCLK_SQUASH_WINDOW_SIZE_MASK	REG_GENMASK(27, 24)









#define  CDCLK_SQUASH_WINDOW_SIZE(x)	REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))









#define  CDCLK_SQUASH_WAVEFORM_MASK	REG_GENMASK(15, 0)









#define  CDCLK_SQUASH_WAVEFORM(x)	REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))

















/* LCPLL_CTL */









#define LCPLL1_CTL		_MMIO(0x46010)









#define LCPLL2_CTL		_MMIO(0x46014)