Loading arch/x86/include/asm/nospec-branch.h +11 −0 Original line number Diff line number Diff line Loading @@ -329,6 +329,17 @@ #endif .endm /* * Macro to execute VERW instruction that mitigate transient data sampling * attacks such as MDS. On affected systems a microcode update overloaded VERW * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. * * Note: Only the memory operand variant of VERW clears the CPU buffers. */ .macro CLEAR_CPU_BUFFERS ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLEAR_CPU_BUF .endm #else /* __ASSEMBLY__ */ #define ANNOTATE_RETPOLINE_SAFE \ Loading Loading
arch/x86/include/asm/nospec-branch.h +11 −0 Original line number Diff line number Diff line Loading @@ -329,6 +329,17 @@ #endif .endm /* * Macro to execute VERW instruction that mitigate transient data sampling * attacks such as MDS. On affected systems a microcode update overloaded VERW * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. * * Note: Only the memory operand variant of VERW clears the CPU buffers. */ .macro CLEAR_CPU_BUFFERS ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLEAR_CPU_BUF .endm #else /* __ASSEMBLY__ */ #define ANNOTATE_RETPOLINE_SAFE \ Loading
