Commit 21772c43 authored by Madalin Bucur's avatar Madalin Bucur Committed by Li Yang
Browse files

soc/fsl/qbman: different register offsets on ARM 



Signed-off-by: default avatarMadalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: default avatarRoy Pledge <roy.pledge@nxp.com>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent 2c62f8b6

drivers/soc/fsl/qbman/bman.c

+22 −0
Original line number Diff line number Diff line
@@ -35,6 +35,27 @@ 


/* Portal register assists */



#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)

/* Cache-inhibited register offsets */

#define BM_REG_RCR_PI_CINH	0x3000

#define BM_REG_RCR_CI_CINH	0x3100

#define BM_REG_RCR_ITR		0x3200

#define BM_REG_CFG		0x3300

#define BM_REG_SCN(n)		(0x3400 + ((n) << 6))

#define BM_REG_ISR		0x3e00

#define BM_REG_IER		0x3e40

#define BM_REG_ISDR		0x3e80

#define BM_REG_IIR		0x3ec0



/* Cache-enabled register offsets */

#define BM_CL_CR		0x0000

#define BM_CL_RR0		0x0100

#define BM_CL_RR1		0x0140

#define BM_CL_RCR		0x1000

#define BM_CL_RCR_PI_CENA	0x3000

#define BM_CL_RCR_CI_CENA	0x3100



#else

/* Cache-inhibited register offsets */

#define BM_REG_RCR_PI_CINH	0x0000

#define BM_REG_RCR_CI_CINH	0x0004
@@ -53,6 +74,7 @@ 
#define BM_CL_RCR		0x1000

#define BM_CL_RCR_PI_CENA	0x3000

#define BM_CL_RCR_CI_CENA	0x3100

#endif



/*

 * Portal modes.

drivers/soc/fsl/qbman/qman.c

+38 −0
Original line number Diff line number Diff line
@@ -41,6 +41,43 @@ 


/* Portal register assists */



#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)

/* Cache-inhibited register offsets */

#define QM_REG_EQCR_PI_CINH	0x3000

#define QM_REG_EQCR_CI_CINH	0x3040

#define QM_REG_EQCR_ITR		0x3080

#define QM_REG_DQRR_PI_CINH	0x3100

#define QM_REG_DQRR_CI_CINH	0x3140

#define QM_REG_DQRR_ITR		0x3180

#define QM_REG_DQRR_DCAP	0x31C0

#define QM_REG_DQRR_SDQCR	0x3200

#define QM_REG_DQRR_VDQCR	0x3240

#define QM_REG_DQRR_PDQCR	0x3280

#define QM_REG_MR_PI_CINH	0x3300

#define QM_REG_MR_CI_CINH	0x3340

#define QM_REG_MR_ITR		0x3380

#define QM_REG_CFG		0x3500

#define QM_REG_ISR		0x3600

#define QM_REG_IER		0x3640

#define QM_REG_ISDR		0x3680

#define QM_REG_IIR		0x36C0

#define QM_REG_ITPR		0x3740



/* Cache-enabled register offsets */

#define QM_CL_EQCR		0x0000

#define QM_CL_DQRR		0x1000

#define QM_CL_MR		0x2000

#define QM_CL_EQCR_PI_CENA	0x3000

#define QM_CL_EQCR_CI_CENA	0x3040

#define QM_CL_DQRR_PI_CENA	0x3100

#define QM_CL_DQRR_CI_CENA	0x3140

#define QM_CL_MR_PI_CENA	0x3300

#define QM_CL_MR_CI_CENA	0x3340

#define QM_CL_CR		0x3800

#define QM_CL_RR0		0x3900

#define QM_CL_RR1		0x3940



#else

/* Cache-inhibited register offsets */

#define QM_REG_EQCR_PI_CINH	0x0000

#define QM_REG_EQCR_CI_CINH	0x0004
@@ -75,6 +112,7 @@ 
#define QM_CL_CR		0x3800

#define QM_CL_RR0		0x3900

#define QM_CL_RR1		0x3940

#endif



/*

 * BTW, the drivers (and h/w programming model) already obtain the required