Commit 2261229c authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add module parameter choose runtime method 



Default runtime logic not changed.
Provide an alternative runtime method. (set 1 to use BACO; 2 to use BAMACO)
When set reset_method to 4, it will use BACO or BAMACO for gpu reset,
according to runpm value.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ddc3344f

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -304,7 +304,7 @@ module_param_named(aspm, amdgpu_aspm, int, 0444); 
 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down

 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.

 */

MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");

MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");

module_param_named(runpm, amdgpu_runtime_pm, int, 0444);



/**
@@ -790,7 +790,7 @@ module_param_named(tmz, amdgpu_tmz, int, 0444); 
 * DOC: reset_method (int)

 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

 */

MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)");

MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");

module_param_named(reset_method, amdgpu_reset_method, int, 0444);



/**

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

+30 −8
Original line number Diff line number Diff line
@@ -1485,6 +1485,9 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) 
	return baco_state;

}



#define D3HOT_BACO_SEQUENCE 0

#define D3HOT_BAMACO_SEQUENCE 2



int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)

{

	struct smu_baco_context *smu_baco = &smu->smu_baco;
@@ -1499,6 +1502,22 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 
	mutex_lock(&smu_baco->mutex);



	if (state == SMU_BACO_STATE_ENTER) {

		switch (adev->asic_type) {

		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_DIMGREY_CAVEFISH:

			if (amdgpu_runtime_pm == 2)

				ret = smu_cmn_send_smc_msg_with_param(smu,

								      SMU_MSG_EnterBaco,

								      D3HOT_BAMACO_SEQUENCE,

								      NULL);

			else

				ret = smu_cmn_send_smc_msg_with_param(smu,

								      SMU_MSG_EnterBaco,

								      D3HOT_BACO_SEQUENCE,

								      NULL);

			break;

		default:

			if (!ras || !ras->supported) {

				data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

				data |= 0x80000000;
@@ -1508,6 +1527,9 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 
			} else {

				ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);

			}

			break;

		}



	} else {

		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);

		if (ret)