Commit 22e2f847 authored by Zong-Zhe Yang's avatar Zong-Zhe Yang Committed by Kalle Valo
Browse files

rtw89: 8852a: update HW setting on BB 



Sometimes, BB might encounter RX problem on OFDM 6M. It's not quite
easy to happen, but if it happens, we will keep getting stuck on RX.
And, since we cannot properly receive layer 2 ACK, it also casues TX
problem, e.g. constantly retrying TX. Eventually, after some time, we
would get disconnected due to abnormal behavior.

Update break setting and phy status parsing time to make BB get out
of stuck state faster.

Signed-off-by: default avatarZong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220704023453.19935-3-pkshih@realtek.com
parent 0e91d191

drivers/net/wireless/realtek/rtw89/reg.h

+2 −1
Original line number Diff line number Diff line
@@ -3426,8 +3426,9 @@ 
#define R_MAC_PIN_SEL 0x0734

#define B_CH_IDX_SEG0 GENMASK(23, 16)

#define R_PLCP_HISTOGRAM 0x0738

#define B_STS_DIS_TRIG_BY_BRK BIT(2)

#define B_STS_PARSING_TIME GENMASK(19, 16)

#define B_STS_DIS_TRIG_BY_FAIL BIT(3)

#define B_STS_DIS_TRIG_BY_BRK BIT(2)

#define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL

#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)

#define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C

drivers/net/wireless/realtek/rtw89/rtw8852a.c

+2 −1
Original line number Diff line number Diff line
@@ -1102,11 +1102,12 @@ static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 
	if (rtwdev->hal.cv <= CHIP_CCV) {

		rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);

		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);

		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F);

		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);

		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);

		rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);

		rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);

		rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);

		rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);

	}

	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);

	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);