Commit 233e6e9d authored by Harini Katakam's avatar Harini Katakam Committed by Michal Simek
Browse files

arm64: zynqmp: Assign TSU clock frequency for GEMs 



Allow changing TSU clock for all GEMs. Kria SOM is using this
functionality that's why set TSU clock frequency as 250MHz (minimum when
running at 1G) to allow PTP functionality.

Signed-off-by: default avatarHarini Katakam <harini.katakam@amd.com>
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b9285b50a2a4abb136ecb0873343a4e84626581.1686228675.git.michal.simek@amd.com
parent 3175b522

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -146,24 +146,28 @@ &gem0 { 
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,

		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,

		 <&zynqmp_clk GEM_TSU>;

	assigned-clocks = <&zynqmp_clk GEM_TSU>;

};



&gem1 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,

		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,

		 <&zynqmp_clk GEM_TSU>;

	assigned-clocks = <&zynqmp_clk GEM_TSU>;

};



&gem2 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,

		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,

		 <&zynqmp_clk GEM_TSU>;

	assigned-clocks = <&zynqmp_clk GEM_TSU>;

};



&gem3 {

	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,

		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,

		 <&zynqmp_clk GEM_TSU>;

	assigned-clocks = <&zynqmp_clk GEM_TSU>;

};



&gpio {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+1 −0
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ &gem3 { /* required by spec */ 
	pinctrl-0 = <&pinctrl_gem3_default>;

	phy-handle = <&phy0>;

	phy-mode = "rgmii-id";

	assigned-clock-rates = <250000000>;



	mdio: mdio {

		#address-cells = <1>;

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+1 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ &gem3 { /* required by spec */ 
	pinctrl-0 = <&pinctrl_gem3_default>;

	phy-handle = <&phy0>;

	phy-mode = "rgmii-id";

	assigned-clock-rates = <250000000>;



	mdio: mdio {

		#address-cells = <1>;