Unverified Commit 23e001e7 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Arnd Bergmann
Browse files

arm64: dts: uniphier: Add ahci controller nodes for PXs3 



Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.

This supports for PXs3 and the boards.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-7-hayashi.kunihiko@socionext.com

'
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 5ba95e8e

arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts

+8 −0
Original line number Diff line number Diff line
@@ -137,6 +137,14 @@ nand@0 { 
	};

};



&ahci0 {

	status = "okay";

};



&ahci1 {

	status = "okay";

};



&pinctrl_ether_rgmii {

	tx {

		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -596,6 +596,86 @@ mdio1: mdio { 
			};

		};



		ahci0: sata@65600000 {

			compatible = "socionext,uniphier-pxs3-ahci",

				     "generic-ahci";

			status = "disabled";

			reg = <0x65600000 0x10000>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sys_clk 28>;

			resets = <&sys_rst 28>, <&ahci0_rst 0>;

			ports-implemented = <1>;

			phys = <&ahci0_phy>;

		};



		sata-controller@65700000 {

			compatible = "socionext,uniphier-pxs3-ahci-glue",

				     "simple-mfd";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x65700000 0x100>;



			ahci0_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pxs3-ahci-reset";

				reg = <0x0 0x4>;

				clock-names = "link";

				clocks = <&sys_clk 28>;

				reset-names = "link";

				resets = <&sys_rst 28>;

				#reset-cells = <1>;

			};



			ahci0_phy: sata-phy@10 {

				compatible = "socionext,uniphier-pxs3-ahci-phy";

				reg = <0x10 0x10>;

				clock-names = "link", "phy";

				clocks = <&sys_clk 28>, <&sys_clk 30>;

				reset-names = "link", "phy";

				resets = <&sys_rst 28>, <&sys_rst 30>;

				#phy-cells = <0>;

			};

		};



		ahci1: sata@65800000 {

			compatible = "socionext,uniphier-pxs3-ahci",

				     "generic-ahci";

			status = "disabled";

			reg = <0x65800000 0x10000>;

			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&sys_clk 29>;

			resets = <&sys_rst 29>, <&ahci1_rst 0>;

			ports-implemented = <1>;

			phys = <&ahci1_phy>;

		};



		sata-controller@65900000 {

			compatible = "socionext,uniphier-pxs3-ahci-glue",

				     "simple-mfd";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x65900000 0x100>;



			ahci1_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pxs3-ahci-reset";

				reg = <0x0 0x4>;

				clock-names = "link";

				clocks = <&sys_clk 29>;

				reset-names = "link";

				resets = <&sys_rst 29>;

				#reset-cells = <1>;

			};



			ahci1_phy: sata-phy@10 {

				compatible = "socionext,uniphier-pxs3-ahci-phy";

				reg = <0x10 0x10>;

				clock-names = "link", "phy";

				clocks = <&sys_clk 29>, <&sys_clk 30>;

				reset-names = "link", "phy";

				resets = <&sys_rst 29>, <&sys_rst 30>;

				#phy-cells = <0>;

			};

		};



		usb0: usb@65a00000 {

			compatible = "socionext,uniphier-dwc3", "snps,dwc3";

			status = "disabled";