Commit 243d3de3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.12-rockchip-dts32-1' of... 

Merge tag 'v5.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Fixed indices for mmc nodes; removal of obsolete amba bus nodes;
addition of nand flash controller odes to rk3036, rk2928, rv1108;
gpu node for rk3288-miqi and some cleanups to make dtbscheck happier.

* tag 'v5.12-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: assign a fixed index to mmc devices on rv1108 boards
  ARM: dts: rockchip: assign a fixed index to mmc devices on rk322x boards
  ARM: dts: rockchip: Remove bogus "amba" bus nodes
  ARM: dts: rockchip: Add NFC node for RK3036 SoC
  ARM: dts: rockchip: Add NFC node for RK2928 and other SoCs
  ARM: dts: rockchip: Add NFC node for RV1108 SoC
  ARM: dts: rockchip: rename thermal subnodes for rk3288
  ARM: dts: rockchip: add QoS register compatibles for rk3288
  ARM: dts: rockchip: add QoS register compatibles for rk3066/rk3188
  ARM: dts: rockchip: add gpu node to rk3288-miqi

Link: https://lore.kernel.org/r/2184150.ElGaqSPkdT@phil


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 74d60e2e 1034e2b6

arch/arm/boot/dts/rk3036.dtsi

+64 −19
Original line number Diff line number Diff line
@@ -54,25 +54,6 @@ cpu1: cpu@f01 { 
		};

	};



	amba: bus {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		pdma: pdma@20078000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x20078000 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMAC2>;

			clock-names = "apb_pclk";

		};

	};



	arm-pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -292,6 +273,21 @@ i2s: i2s@10220000 { 
		status = "disabled";

	};



	nfc: nand-controller@10500000 {

		compatible = "rockchip,rk3036-nfc",

			     "rockchip,rk2928-nfc";

		reg = <0x10500000 0x4000>;

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;

		clock-names = "ahb", "nfc";

		assigned-clocks = <&cru SCLK_NANDC>;

		assigned-clock-rates = <150000000>;

		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0

			     &flash_rdn &flash_rdy &flash_wrn>;

		pinctrl-names = "default";

		status = "disabled";

	};



	cru: clock-controller@20000000 {

		compatible = "rockchip,rk3036-cru";

		reg = <0x20000000 0x1000>;
@@ -494,6 +490,18 @@ spi: spi@20074000 { 
		status = "disabled";

	};



	pdma: pdma@20078000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x20078000 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMAC2>;

		clock-names = "apb_pclk";

	};



	pinctrl: pinctrl {

		compatible = "rockchip,rk3036-pinctrl";

		rockchip,grf = <&grf>;
@@ -643,6 +651,43 @@ emmc_bus8: emmc-bus8 { 
			};

		};



		nfc {

			flash_ale: flash-ale {

				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;

			};



			flash_bus8: flash-bus8 {

				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,

						<1 RK_PD1 1 &pcfg_pull_default>,

						<1 RK_PD2 1 &pcfg_pull_default>,

						<1 RK_PD3 1 &pcfg_pull_default>,

						<1 RK_PD4 1 &pcfg_pull_default>,

						<1 RK_PD5 1 &pcfg_pull_default>,

						<1 RK_PD6 1 &pcfg_pull_default>,

						<1 RK_PD7 1 &pcfg_pull_default>;

			};



			flash_cle: flash-cle {

				rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;

			};



			flash_csn0: flash-csn0 {

				rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;

			};



			flash_rdn: flash-rdn {

				rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;

			};



			flash_rdy: flash-rdy {

				rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;

			};



			flash_wrn: flash-wrn {

				rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;

			};

		};



		emac {

			emac_xfer: emac-xfer {

				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */

arch/arm/boot/dts/rk322x.dtsi

+14 −18
Original line number Diff line number Diff line
@@ -14,6 +14,9 @@ / { 
	interrupt-parent = <&gic>;



	aliases {

		mmc0 = &sdmmc;

		mmc1 = &sdio;

		mmc2 = &emmc;

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;
@@ -95,24 +98,6 @@ opp-1200000000 { 
		};

	};



	amba: bus {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		pdma: pdma@110f0000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x110f0000 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMAC>;

			clock-names = "apb_pclk";

		};

	};



	arm-pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -464,6 +449,17 @@ cru: clock-controller@110e0000 { 
			<75000000>;

	};



	pdma: pdma@110f0000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x110f0000 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMAC>;

		clock-names = "apb_pclk";

	};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <100>; /* milliseconds */

arch/arm/boot/dts/rk3288-miqi.dts

+5 −0
Original line number Diff line number Diff line
@@ -123,6 +123,11 @@ &gmac { 
	status = "okay";

};



&gpu {

	mali-supply = <&vdd_gpu>;

	status = "okay";

};



&hdmi {

	ddc-i2c-bus = <&i2c5>;

	status = "okay";

arch/arm/boot/dts/rk3288.dtsi

+54 −61
Original line number Diff line number Diff line
@@ -154,50 +154,6 @@ opp-1608000000 { 
		};

	};



	amba: bus {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		dmac_peri: dma-controller@ff250000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x0 0xff250000 0x0 0x4000>;

			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMAC2>;

			clock-names = "apb_pclk";

		};



		dmac_bus_ns: dma-controller@ff600000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x0 0xff600000 0x0 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMAC1>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dmac_bus_s: dma-controller@ffb20000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x0 0xffb20000 0x0 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMAC1>;

			clock-names = "apb_pclk";

		};

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -487,15 +443,27 @@ uart4: serial@ff1c0000 { 
		status = "disabled";

	};



	dmac_peri: dma-controller@ff250000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x0 0xff250000 0x0 0x4000>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMAC2>;

		clock-names = "apb_pclk";

	};



	thermal-zones {

		reserve_thermal: reserve_thermal {

		reserve_thermal: reserve-thermal {

			polling-delay-passive = <1000>; /* milliseconds */

			polling-delay = <5000>; /* milliseconds */



			thermal-sensors = <&tsadc 0>;

		};



		cpu_thermal: cpu_thermal {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <100>; /* milliseconds */

			polling-delay = <5000>; /* milliseconds */
@@ -539,7 +507,7 @@ map1 { 
			};

		};



		gpu_thermal: gpu_thermal {

		gpu_thermal: gpu-thermal {

			polling-delay-passive = <100>; /* milliseconds */

			polling-delay = <5000>; /* milliseconds */
@@ -665,6 +633,19 @@ usb_hsic: usb@ff5c0000 { 
		status = "disabled";

	};



	dmac_bus_ns: dma-controller@ff600000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x0 0xff600000 0x0 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMAC1>;

		clock-names = "apb_pclk";

		status = "disabled";

	};



	i2c0: i2c@ff650000 {

		compatible = "rockchip,rk3288-i2c";

		reg = <0x0 0xff650000 0x0 0x1000>;
@@ -1329,75 +1310,87 @@ opp-600000000 { 
	};



	qos_gpu_r: qos@ffaa0000 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffaa0000 0x0 0x20>;

	};



	qos_gpu_w: qos@ffaa0080 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffaa0080 0x0 0x20>;

	};



	qos_vio1_vop: qos@ffad0000 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0000 0x0 0x20>;

	};



	qos_vio1_isp_w0: qos@ffad0100 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0100 0x0 0x20>;

	};



	qos_vio1_isp_w1: qos@ffad0180 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0180 0x0 0x20>;

	};



	qos_vio0_vop: qos@ffad0400 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0400 0x0 0x20>;

	};



	qos_vio0_vip: qos@ffad0480 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0480 0x0 0x20>;

	};



	qos_vio0_iep: qos@ffad0500 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0500 0x0 0x20>;

	};



	qos_vio2_rga_r: qos@ffad0800 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0800 0x0 0x20>;

	};



	qos_vio2_rga_w: qos@ffad0880 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0880 0x0 0x20>;

	};



	qos_vio1_isp_r: qos@ffad0900 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffad0900 0x0 0x20>;

	};



	qos_video: qos@ffae0000 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffae0000 0x0 0x20>;

	};



	qos_hevc_r: qos@ffaf0000 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffaf0000 0x0 0x20>;

	};



	qos_hevc_w: qos@ffaf0080 {

		compatible = "syscon";

		compatible = "rockchip,rk3288-qos", "syscon";

		reg = <0x0 0xffaf0080 0x0 0x20>;

	};



	dmac_bus_s: dma-controller@ffb20000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x0 0xffb20000 0x0 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMAC1>;

		clock-names = "apb_pclk";

	};



	efuse: efuse@ffb40000 {

		compatible = "rockchip,rk3288-efuse";

		reg = <0x0 0xffb40000 0x0 0x20>;

arch/arm/boot/dts/rk3xxx.dtsi

+54 −52
Original line number Diff line number Diff line
@@ -32,50 +32,6 @@ aliases { 
		spi1 = &spi1;

	};



	amba: bus {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		dmac1_s: dma-controller@20018000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x20018000 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMA1>;

			clock-names = "apb_pclk";

		};



		dmac1_ns: dma-controller@2001c000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x2001c000 0x4000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMA1>;

			clock-names = "apb_pclk";

			status = "disabled";

		};



		dmac2: dma-controller@20078000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x20078000 0x4000>;

			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			arm,pl330-broken-no-flushp;

			arm,pl330-periph-burst;

			clocks = <&cru ACLK_DMA2>;

			clock-names = "apb_pclk";

		};

	};



	xin24m: oscillator {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;
@@ -151,42 +107,42 @@ uart1: serial@10126000 { 
	};



	qos_gpu: qos@1012d000 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012d000 0x20>;

	};



	qos_vpu: qos@1012e000 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012e000 0x20>;

	};



	qos_lcdc0: qos@1012f000 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f000 0x20>;

	};



	qos_cif0: qos@1012f080 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f080 0x20>;

	};



	qos_ipp: qos@1012f100 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f100 0x20>;

	};



	qos_lcdc1: qos@1012f180 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f180 0x20>;

	};



	qos_cif1: qos@1012f200 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f200 0x20>;

	};



	qos_rga: qos@1012f280 {

		compatible = "syscon";

		compatible = "rockchip,rk3066-qos", "syscon";

		reg = <0x1012f280 0x20>;

	};
@@ -276,6 +232,15 @@ emmc: mmc@1021c000 { 
		status = "disabled";

	};



	nfc: nand-controller@10500000 {

		compatible = "rockchip,rk2928-nfc";

		reg = <0x10500000 0x4000>;

		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_NANDC0>;

		clock-names = "ahb";

		status = "disabled";

	};



	pmu: pmu@20004000 {

		compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";

		reg = <0x20004000 0x100>;
@@ -295,6 +260,31 @@ grf: grf@20008000 { 
		reg = <0x20008000 0x200>;

	};



	dmac1_s: dma-controller@20018000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x20018000 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMA1>;

		clock-names = "apb_pclk";

	};



	dmac1_ns: dma-controller@2001c000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x2001c000 0x4000>;

		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMA1>;

		clock-names = "apb_pclk";

		status = "disabled";

	};



	i2c0: i2c@2002d000 {

		compatible = "rockchip,rk3066-i2c";

		reg = <0x2002d000 0x1000>;
@@ -469,4 +459,16 @@ spi1: spi@20074000 { 
		dma-names = "tx", "rx";

		status = "disabled";

	};



	dmac2: dma-controller@20078000 {

		compatible = "arm,pl330", "arm,primecell";

		reg = <0x20078000 0x4000>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

		#dma-cells = <1>;

		arm,pl330-broken-no-flushp;

		arm,pl330-periph-burst;

		clocks = <&cru ACLK_DMA2>;

		clock-names = "apb_pclk";

	};

};