Commit 24a5993e authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Rob Clark
Browse files

drm/msm/dsi: update dsi register header file for tpg 



Update the DSI controller header XML file to add registers
and bitfields to support rectangular checkered pattern
generator.

Signed-off-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/1626922232-29105-1-git-send-email-abhinavk@codeaurora.org


Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
[DB: removed headergen commit changes]
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 65c391b3

drivers/gpu/drm/msm/dsi/dsi.xml.h

+73 −0
Original line number Diff line number Diff line
@@ -105,6 +105,32 @@ enum dsi_lane_swap { 
	LANE_SWAP_3210 = 7,

};



enum video_config_bpp {

	VIDEO_CONFIG_18BPP = 0,

	VIDEO_CONFIG_24BPP = 1,

};



enum video_pattern_sel {

	VID_PRBS = 0,

	VID_INCREMENTAL = 1,

	VID_FIXED = 2,

	VID_MDSS_GENERAL_PATTERN = 3,

};



enum cmd_mdp_stream0_pattern_sel {

	CMD_MDP_PRBS = 0,

	CMD_MDP_INCREMENTAL = 1,

	CMD_MDP_FIXED = 2,

	CMD_MDP_MDSS_GENERAL_PATTERN = 3,

};



enum cmd_dma_pattern_sel {

	CMD_DMA_PRBS = 0,

	CMD_DMA_INCREMENTAL = 1,

	CMD_DMA_FIXED = 2,

	CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3,

};



#define DSI_IRQ_CMD_DMA_DONE					0x00000001

#define DSI_IRQ_MASK_CMD_DMA_DONE				0x00000002

#define DSI_IRQ_CMD_MDP_DONE					0x00000100
@@ -564,6 +590,53 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 
#define REG_DSI_PHY_RESET					0x00000128

#define DSI_PHY_RESET_RESET					0x00000001



#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL			0x00000160



#define REG_DSI_TPG_MAIN_CONTROL				0x00000198

#define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN	0x00000100



#define REG_DSI_TPG_VIDEO_CONFIG				0x000001a0

#define DSI_TPG_VIDEO_CONFIG_BPP__MASK				0x00000003

#define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT				0

static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val)

{

	return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK;

}

#define DSI_TPG_VIDEO_CONFIG_RGB				0x00000004



#define REG_DSI_TEST_PATTERN_GEN_CTRL				0x00000158

#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK	0x00030000

#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT	16

static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val)

{

	return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK;

}

#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK	0x00000300

#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT	8

static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val)

{

	return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK;

}

#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK	0x00000030

#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT	4

static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val)

{

	return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK;

}

#define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE		0x00000004

#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN		0x00000002

#define DSI_TEST_PATTERN_GEN_CTRL_EN				0x00000001



#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0		0x00000168



#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER		0x00000180

#define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER	0x00000001



#define REG_DSI_TPG_MAIN_CONTROL2				0x0000019c

#define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN	0x00000080

#define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN	0x00010000

#define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN	0x02000000



#define REG_DSI_T_CLK_PRE_EXTEND				0x0000017c

#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK			0x00000001