Commit 254a2758 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
Browse files

ARM: dts: qcom: sdx55: Add support for PCIe PHY 



Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is
used by the PCIe EP controller.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211126070520.28979-2-manivannan.sadhasivam@linaro.org
parent 801cd261

arch/arm/boot/dts/qcom-sdx55.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -309,6 +309,41 @@ qpic_nand: nand-controller@1b30000 { 
			status = "disabled";

		};



		pcie0_phy: phy@1c07000 {

			compatible = "qcom,sdx55-qmp-pcie-phy";

			reg = <0x01c07000 0x1c4>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,

				 <&gcc GCC_PCIE_CFG_AHB_CLK>,

				 <&gcc GCC_PCIE_0_CLKREF_CLK>,

				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;

			clock-names = "aux", "cfg_ahb", "ref", "refgen";



			resets = <&gcc GCC_PCIE_PHY_BCR>;

			reset-names = "phy";



			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;

			assigned-clock-rates = <100000000>;



			status = "disabled";



			pcie0_lane: lanes@1c06000 {

				reg = <0x01c06000 0x104>, /* tx0 */

				      <0x01c06200 0x328>, /* rx0 */

				      <0x01c07200 0x1e8>, /* pcs */

				      <0x01c06800 0x104>, /* tx1 */

				      <0x01c06a00 0x328>, /* rx1 */

				      <0x01c07600 0x800>; /* pcs_misc */

				clocks = <&gcc GCC_PCIE_PIPE_CLK>;

				clock-names = "pipe0";



				#phy-cells = <0>;

				clock-output-names = "pcie_pipe_clk";

			};

		};



		ipa: ipa@1e40000 {

			compatible = "qcom,sdx55-ipa";