Commit 2562dc42 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock 



Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Tested-by: default avatarDaniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 6b7daeaa

drivers/clk/mediatek/clk-mt7986-apmixed.c

+1 −3
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
		 "clkxtal")



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,

	    0x0200, 4, 0, 0x0204, 0),

	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,

	    0x0210, 4, 0, 0x0214, 0),
@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev) 


	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);



	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r) {

		pr_err("%s(): could not register clock provider: %d\n",