Commit 2566ad8e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
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phy: qcom-qmp-pcie: split register tables into common and extra parts 



SM8250 configuration tables are split into two parts: the common one and
the PHY-specific tables. Make this split more formal. Rather than having
a blind renamed copy of all QMP table fields, add separate struct
qmp_phy_cfg_tables and add two instances of this structure to the struct
qmp_phy_cfg. Later on this will be used to support different PHY modes
(RC vs EP).

Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220927092207.161501-2-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent b01d622d

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+222 −184
Original line number Diff line number Diff line
@@ -1300,31 +1300,30 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),

};



struct qmp_phy_cfg_tables {

	const struct qmp_phy_init_tbl *serdes;

	int serdes_num;

	const struct qmp_phy_init_tbl *tx;

	int tx_num;

	const struct qmp_phy_init_tbl *rx;

	int rx_num;

	const struct qmp_phy_init_tbl *pcs;

	int pcs_num;

	const struct qmp_phy_init_tbl *pcs_misc;

	int pcs_misc_num;

};



/* struct qmp_phy_cfg - per-PHY initialization config */

struct qmp_phy_cfg {

	int lanes;



	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */

	const struct qmp_phy_init_tbl *serdes_tbl;

	int serdes_tbl_num;

	const struct qmp_phy_init_tbl *serdes_tbl_sec;

	int serdes_tbl_num_sec;

	const struct qmp_phy_init_tbl *tx_tbl;

	int tx_tbl_num;

	const struct qmp_phy_init_tbl *tx_tbl_sec;

	int tx_tbl_num_sec;

	const struct qmp_phy_init_tbl *rx_tbl;

	int rx_tbl_num;

	const struct qmp_phy_init_tbl *rx_tbl_sec;

	int rx_tbl_num_sec;

	const struct qmp_phy_init_tbl *pcs_tbl;

	int pcs_tbl_num;

	const struct qmp_phy_init_tbl *pcs_tbl_sec;

	int pcs_tbl_num_sec;

	const struct qmp_phy_init_tbl *pcs_misc_tbl;

	int pcs_misc_tbl_num;

	const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;

	int pcs_misc_tbl_num_sec;

	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */

	const struct qmp_phy_cfg_tables tables;

	/*

	 * Additional init sequence for PHY blocks, providing additional

	 * register programming. Unless required it can be left omitted.

	 */

	const struct qmp_phy_cfg_tables *tables_rc;



	/* clock ids to be requested */

	const char * const *clk_list;
@@ -1459,14 +1458,16 @@ static const char * const sdm845_pciephy_reset_l[] = { 
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= ipq8074_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_pcie_serdes_tbl),

	.tx_tbl			= ipq8074_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_tx_tbl),

	.rx_tbl			= ipq8074_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_rx_tbl),

	.pcs_tbl		= ipq8074_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),

	.tables = {

		.serdes		= ipq8074_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(ipq8074_pcie_serdes_tbl),

		.tx		= ipq8074_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(ipq8074_pcie_tx_tbl),

		.rx		= ipq8074_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(ipq8074_pcie_rx_tbl),

		.pcs		= ipq8074_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),

	},

	.clk_list		= ipq8074_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,
@@ -1487,14 +1488,16 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 
static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {

	.lanes			= 1,



	.serdes_tbl		= ipq8074_pcie_gen3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),

	.tx_tbl			= ipq8074_pcie_gen3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),

	.rx_tbl			= ipq8074_pcie_gen3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),

	.pcs_tbl		= ipq8074_pcie_gen3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),

	.tables = {

		.serdes		= ipq8074_pcie_gen3_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),

		.tx		= ipq8074_pcie_gen3_tx_tbl,

		.tx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),

		.rx		= ipq8074_pcie_gen3_rx_tbl,

		.rx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),

		.pcs		= ipq8074_pcie_gen3_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),

	},

	.clk_list		= ipq8074_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,
@@ -1516,16 +1519,18 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= ipq6018_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(ipq6018_pcie_serdes_tbl),

	.tx_tbl			= ipq6018_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),

	.rx_tbl			= ipq6018_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(ipq6018_pcie_rx_tbl),

	.pcs_tbl		= ipq6018_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),

	.pcs_misc_tbl		= ipq6018_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= ipq6018_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(ipq6018_pcie_serdes_tbl),

		.tx		= ipq6018_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),

		.rx		= ipq6018_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(ipq6018_pcie_rx_tbl),

		.pcs		= ipq6018_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),

		.pcs_misc	= ipq6018_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),

	},

	.clk_list		= ipq8074_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(ipq8074_pciephy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,
@@ -1545,16 +1550,18 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= sdm845_qmp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),

	.tx_tbl			= sdm845_qmp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),

	.rx_tbl			= sdm845_qmp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),

	.pcs_tbl		= sdm845_qmp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),

	.pcs_misc_tbl		= sdm845_qmp_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sdm845_qmp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),

		.tx		= sdm845_qmp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),

		.rx		= sdm845_qmp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),

		.pcs		= sdm845_qmp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),

		.pcs_misc	= sdm845_qmp_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1575,14 +1582,16 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 
static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= sdm845_qhp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),

	.tx_tbl			= sdm845_qhp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),

	.rx_tbl			= sdm845_qhp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),

	.pcs_tbl		= sdm845_qhp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),

	.tables = {

		.serdes		= sdm845_qhp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),

		.tx		= sdm845_qhp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),

		.rx		= sdm845_qhp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),

		.pcs		= sdm845_qhp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1603,24 +1612,28 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= sm8250_qmp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),

	.serdes_tbl_sec		= sm8250_qmp_gen3x1_pcie_serdes_tbl,

	.serdes_tbl_num_sec	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),

	.tx_tbl			= sm8250_qmp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),

	.rx_tbl			= sm8250_qmp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),

	.rx_tbl_sec		= sm8250_qmp_gen3x1_pcie_rx_tbl,

	.rx_tbl_num_sec		= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),

	.pcs_tbl		= sm8250_qmp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),

	.pcs_tbl_sec		= sm8250_qmp_gen3x1_pcie_pcs_tbl,

	.pcs_tbl_num_sec		= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),

	.pcs_misc_tbl		= sm8250_qmp_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),

	.pcs_misc_tbl_sec		= sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num_sec	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sm8250_qmp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),

		.tx		= sm8250_qmp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),

		.rx		= sm8250_qmp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),

		.pcs		= sm8250_qmp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),

		.pcs_misc	= sm8250_qmp_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),

	},

	.tables_rc = &(const struct qmp_phy_cfg_tables) {

		.serdes		= sm8250_qmp_gen3x1_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),

		.rx		= sm8250_qmp_gen3x1_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),

		.pcs		= sm8250_qmp_gen3x1_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),

		.pcs_misc	= sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1641,24 +1654,28 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {

	.lanes			= 2,



	.serdes_tbl		= sm8250_qmp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),

	.tx_tbl			= sm8250_qmp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),

	.tx_tbl_sec		= sm8250_qmp_gen3x2_pcie_tx_tbl,

	.tx_tbl_num_sec		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),

	.rx_tbl			= sm8250_qmp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),

	.rx_tbl_sec		= sm8250_qmp_gen3x2_pcie_rx_tbl,

	.rx_tbl_num_sec		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),

	.pcs_tbl		= sm8250_qmp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),

	.pcs_tbl_sec		= sm8250_qmp_gen3x2_pcie_pcs_tbl,

	.pcs_tbl_num_sec		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),

	.pcs_misc_tbl		= sm8250_qmp_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),

	.pcs_misc_tbl_sec		= sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num_sec	= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sm8250_qmp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),

		.tx		= sm8250_qmp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),

		.rx		= sm8250_qmp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),

		.pcs		= sm8250_qmp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),

		.pcs_misc	= sm8250_qmp_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),

	},

	.tables_rc = &(const struct qmp_phy_cfg_tables) {

		.tx		= sm8250_qmp_gen3x2_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),

		.rx		= sm8250_qmp_gen3x2_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),

		.pcs		= sm8250_qmp_gen3x2_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),

		.pcs_misc	= sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1679,14 +1696,16 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= msm8998_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(msm8998_pcie_serdes_tbl),

	.tx_tbl			= msm8998_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(msm8998_pcie_tx_tbl),

	.rx_tbl			= msm8998_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(msm8998_pcie_rx_tbl),

	.pcs_tbl		= msm8998_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(msm8998_pcie_pcs_tbl),

	.tables = {

		.serdes		= msm8998_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(msm8998_pcie_serdes_tbl),

		.tx		= msm8998_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(msm8998_pcie_tx_tbl),

		.rx		= msm8998_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(msm8998_pcie_rx_tbl),

		.pcs		= msm8998_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(msm8998_pcie_pcs_tbl),

	},

	.clk_list		= msm8996_phy_clk_l,

	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),

	.reset_list		= ipq8074_pciephy_reset_l,
@@ -1703,16 +1722,18 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= sc8180x_qmp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),

	.tx_tbl			= sc8180x_qmp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),

	.rx_tbl			= sc8180x_qmp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),

	.pcs_tbl		= sc8180x_qmp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),

	.pcs_misc_tbl		= sc8180x_qmp_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sc8180x_qmp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),

		.tx		= sc8180x_qmp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),

		.rx		= sc8180x_qmp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),

		.pcs		= sc8180x_qmp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),

		.pcs_misc	= sc8180x_qmp_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1732,16 +1753,18 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 
static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {

	.lanes			= 2,



	.serdes_tbl		= sdx55_qmp_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),

	.tx_tbl			= sdx55_qmp_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),

	.rx_tbl			= sdx55_qmp_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),

	.pcs_tbl		= sdx55_qmp_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),

	.pcs_misc_tbl		= sdx55_qmp_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sdx55_qmp_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),

		.tx		= sdx55_qmp_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),

		.rx		= sdx55_qmp_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),

		.pcs		= sdx55_qmp_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),

		.pcs_misc	= sdx55_qmp_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1762,16 +1785,18 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {

	.lanes			= 1,



	.serdes_tbl		= sm8450_qmp_gen3x1_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),

	.tx_tbl			= sm8450_qmp_gen3x1_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),

	.rx_tbl			= sm8450_qmp_gen3x1_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),

	.pcs_tbl		= sm8450_qmp_gen3x1_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),

	.pcs_misc_tbl		= sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sm8450_qmp_gen3x1_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),

		.tx		= sm8450_qmp_gen3x1_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),

		.rx		= sm8450_qmp_gen3x1_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),

		.pcs		= sm8450_qmp_gen3x1_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),

		.pcs_misc	= sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1792,16 +1817,18 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 
static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {

	.lanes			= 2,



	.serdes_tbl		= sm8450_qmp_gen4x2_pcie_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),

	.tx_tbl			= sm8450_qmp_gen4x2_pcie_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),

	.rx_tbl			= sm8450_qmp_gen4x2_pcie_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),

	.pcs_tbl		= sm8450_qmp_gen4x2_pcie_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),

	.pcs_misc_tbl		= sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,

	.pcs_misc_tbl_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),

	.tables = {

		.serdes		= sm8450_qmp_gen4x2_pcie_serdes_tbl,

		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),

		.tx		= sm8450_qmp_gen4x2_pcie_tx_tbl,

		.tx_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),

		.rx		= sm8450_qmp_gen4x2_pcie_rx_tbl,

		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),

		.pcs		= sm8450_qmp_gen4x2_pcie_pcs_tbl,

		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),

		.pcs_misc	= sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,

		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),

	},

	.clk_list		= sdm845_pciephy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_pciephy_clk_l),

	.reset_list		= sdm845_pciephy_reset_l,
@@ -1850,17 +1877,49 @@ static void qmp_pcie_configure(void __iomem *base, 
	qmp_pcie_configure_lane(base, regs, tbl, num, 0xff);

}



static int qmp_pcie_serdes_init(struct qmp_phy *qphy)

static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)

{

	const struct qmp_phy_cfg *cfg = qphy->cfg;

	void __iomem *serdes = qphy->serdes;

	const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;

	int serdes_tbl_num = cfg->serdes_tbl_num;



	qmp_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);

	qmp_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec);

	if (!tables)

		return;



	return 0;

	qmp_pcie_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num);

}



static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)

{

	const struct qmp_phy_cfg *cfg = qphy->cfg;

	void __iomem *tx = qphy->tx;

	void __iomem *rx = qphy->rx;



	if (!tables)

		return;



	qmp_pcie_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1);



	if (cfg->lanes >= 2)

		qmp_pcie_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num, 2);



	qmp_pcie_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1);

	if (cfg->lanes >= 2)

		qmp_pcie_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num, 2);

}



static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)

{

	const struct qmp_phy_cfg *cfg = qphy->cfg;

	void __iomem *pcs = qphy->pcs;

	void __iomem *pcs_misc = qphy->pcs_misc;



	if (!tables)

		return;



	qmp_pcie_configure(pcs, cfg->regs,

			   tables->pcs, tables->pcs_num);

	qmp_pcie_configure(pcs_misc, cfg->regs,

			   tables->pcs_misc, tables->pcs_misc_num);

}



static int qmp_pcie_init(struct phy *phy)
@@ -1932,15 +1991,13 @@ static int qmp_pcie_power_on(struct phy *phy) 
	struct qmp_phy *qphy = phy_get_drvdata(phy);

	struct qcom_qmp *qmp = qphy->qmp;

	const struct qmp_phy_cfg *cfg = qphy->cfg;

	void __iomem *tx = qphy->tx;

	void __iomem *rx = qphy->rx;

	void __iomem *pcs = qphy->pcs;

	void __iomem *pcs_misc = qphy->pcs_misc;

	void __iomem *status;

	unsigned int mask, val, ready;

	int ret;



	qmp_pcie_serdes_init(qphy);

	qmp_pcie_serdes_init(qphy, &cfg->tables);

	qmp_pcie_serdes_init(qphy, cfg->tables_rc);



	ret = clk_prepare_enable(qphy->pipe_clk);

	if (ret) {
@@ -1949,31 +2006,11 @@ static int qmp_pcie_power_on(struct phy *phy) 
	}



	/* Tx, Rx, and PCS configurations */

	qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);

	qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1);



	if (cfg->lanes >= 2) {

		qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl,

					cfg->tx_tbl_num, 2);

		qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec,

					cfg->tx_tbl_num_sec, 2);

	}



	qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);

	qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);



	if (cfg->lanes >= 2) {

		qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl,

					cfg->rx_tbl_num, 2);

		qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec,

					cfg->rx_tbl_num_sec, 2);

	}



	qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);

	qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec);

	qmp_pcie_lanes_init(qphy, &cfg->tables);

	qmp_pcie_lanes_init(qphy, cfg->tables_rc);



	qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num);

	qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec);

	qmp_pcie_pcs_init(qphy, &cfg->tables);

	qmp_pcie_pcs_init(qphy, cfg->tables_rc);



	/*

	 * Pull out PHY from POWER DOWN state.
@@ -2240,7 +2277,8 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 
		qphy->pcs_misc = qphy->pcs + 0x400;



	if (IS_ERR(qphy->pcs_misc)) {

		if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec)

		if (cfg->tables.pcs_misc ||

		    (cfg->tables_rc && cfg->tables_rc->pcs_misc))

			return PTR_ERR(qphy->pcs_misc);

	}