Commit 25caed3d authored by Richard Zhu's avatar Richard Zhu Committed by Vinod Koul
Browse files

dt-binding: phy: Add i.MX8MP PCIe PHY binding 



Add i.MX8MP PCIe PHY binding.
On i.MX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarRichard Leitner <richard.leitner@skidata.com>
Tested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1665625622-20551-2-git-send-email-hongxing.zhu@nxp.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e27ecef8

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

+13 −3
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ properties: 
  compatible:

    enum:

      - fsl,imx8mm-pcie-phy

      - fsl,imx8mp-pcie-phy



  reg:

    maxItems: 1
@@ -28,11 +29,16 @@ properties: 
      - const: ref



  resets:

    maxItems: 1

    minItems: 1

    maxItems: 2



  reset-names:

    items:

    oneOf:

      - items:          # for iMX8MM

          - const: pciephy

      - items:          # for IMX8MP

          - const: pciephy

          - const: perst



  fsl,refclk-pad-mode:

    description: |
@@ -60,6 +66,10 @@ properties: 
    description: A boolean property indicating the CLKREQ# signal is

      not supported in the board design (optional)



  power-domains:

    description: PCIe PHY  power domain (optional).

    maxItems: 1



required:

  - "#phy-cells"

  - compatible