Commit 25e289e1 authored by Aditya Kumar Singh's avatar Aditya Kumar Singh Committed by Kalle Valo
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wifi: ath11k: use proper regulatory reference for bands



Currently, during regulatory event, 2 GHz/5 GHz is referred
to as 2G/5G including variable names. However, there is no
such entity as 2G or 5G.

Re-name such occurences to its proper name. No functional changes.

Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1

Signed-off-by: default avatarAditya Kumar Singh <quic_adisi@quicinc.com>
Signed-off-by: default avatarKalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20230110121024.14051-2-quic_adisi@quicinc.com
parent 01c6c9fc
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+10 −10
Original line number Diff line number Diff line
@@ -619,7 +619,7 @@ ath11k_reg_build_regd(struct ath11k_base *ab,
	u32 flags;
	char alpha2[3];

	num_rules = reg_info->num_5g_reg_rules + reg_info->num_2g_reg_rules;
	num_rules = reg_info->num_5ghz_reg_rules + reg_info->num_2ghz_reg_rules;

	if (!num_rules)
		goto ret;
@@ -644,20 +644,20 @@ ath11k_reg_build_regd(struct ath11k_base *ab,
		   alpha2, ath11k_reg_get_regdom_str(tmp_regd->dfs_region),
		   reg_info->dfs_region, num_rules);
	/* Update reg_rules[] below. Firmware is expected to
	 * send these rules in order(2G rules first and then 5G)
	 * send these rules in order(2 GHz rules first and then 5 GHz)
	 */
	for (; i < num_rules; i++) {
		if (reg_info->num_2g_reg_rules &&
		    (i < reg_info->num_2g_reg_rules)) {
			reg_rule = reg_info->reg_rules_2g_ptr + i;
		if (reg_info->num_2ghz_reg_rules &&
		    (i < reg_info->num_2ghz_reg_rules)) {
			reg_rule = reg_info->reg_rules_2ghz_ptr + i;
			max_bw = min_t(u16, reg_rule->max_bw,
				       reg_info->max_bw_2g);
				       reg_info->max_bw_2ghz);
			flags = 0;
		} else if (reg_info->num_5g_reg_rules &&
			   (j < reg_info->num_5g_reg_rules)) {
			reg_rule = reg_info->reg_rules_5g_ptr + j++;
		} else if (reg_info->num_5ghz_reg_rules &&
			   (j < reg_info->num_5ghz_reg_rules)) {
			reg_rule = reg_info->reg_rules_5ghz_ptr + j++;
			max_bw = min_t(u16, reg_rule->max_bw,
				       reg_info->max_bw_5g);
				       reg_info->max_bw_5ghz);

			/* FW doesn't pass NL80211_RRF_AUTO_BW flag for
			 * BW Auto correction, we can enable this by default
+30 −28
Original line number Diff line number Diff line
@@ -4959,7 +4959,7 @@ static int ath11k_pull_reg_chan_list_update_ev(struct ath11k_base *ab,
	const void **tb;
	const struct wmi_reg_chan_list_cc_event *chan_list_event_hdr;
	struct wmi_regulatory_rule_struct *wmi_reg_rule;
	u32 num_2g_reg_rules, num_5g_reg_rules;
	u32 num_2ghz_reg_rules, num_5ghz_reg_rules;
	int ret;

	ath11k_dbg(ab, ATH11K_DBG_WMI, "processing regulatory channel list\n");
@@ -4978,10 +4978,10 @@ static int ath11k_pull_reg_chan_list_update_ev(struct ath11k_base *ab,
		return -EPROTO;
	}

	reg_info->num_2g_reg_rules = chan_list_event_hdr->num_2g_reg_rules;
	reg_info->num_5g_reg_rules = chan_list_event_hdr->num_5g_reg_rules;
	reg_info->num_2ghz_reg_rules = chan_list_event_hdr->num_2ghz_reg_rules;
	reg_info->num_5ghz_reg_rules = chan_list_event_hdr->num_5ghz_reg_rules;

	if (!(reg_info->num_2g_reg_rules + reg_info->num_5g_reg_rules)) {
	if (!(reg_info->num_2ghz_reg_rules + reg_info->num_5ghz_reg_rules)) {
		ath11k_warn(ab, "No regulatory rules available in the event info\n");
		kfree(tb);
		return -EINVAL;
@@ -5008,46 +5008,48 @@ static int ath11k_pull_reg_chan_list_update_ev(struct ath11k_base *ab,
	else if (chan_list_event_hdr->status_code == WMI_REG_SET_CC_STATUS_FAIL)
		reg_info->status_code = REG_SET_CC_STATUS_FAIL;

	reg_info->min_bw_2g = chan_list_event_hdr->min_bw_2g;
	reg_info->max_bw_2g = chan_list_event_hdr->max_bw_2g;
	reg_info->min_bw_5g = chan_list_event_hdr->min_bw_5g;
	reg_info->max_bw_5g = chan_list_event_hdr->max_bw_5g;
	reg_info->min_bw_2ghz = chan_list_event_hdr->min_bw_2ghz;
	reg_info->max_bw_2ghz = chan_list_event_hdr->max_bw_2ghz;
	reg_info->min_bw_5ghz = chan_list_event_hdr->min_bw_5ghz;
	reg_info->max_bw_5ghz = chan_list_event_hdr->max_bw_5ghz;

	num_2g_reg_rules = reg_info->num_2g_reg_rules;
	num_5g_reg_rules = reg_info->num_5g_reg_rules;
	num_2ghz_reg_rules = reg_info->num_2ghz_reg_rules;
	num_5ghz_reg_rules = reg_info->num_5ghz_reg_rules;

	ath11k_dbg(ab, ATH11K_DBG_WMI,
		   "%s:cc %s dsf %d BW: min_2g %d max_2g %d min_5g %d max_5g %d",
		   "%s:cc %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d",
		   __func__, reg_info->alpha2, reg_info->dfs_region,
		   reg_info->min_bw_2g, reg_info->max_bw_2g,
		   reg_info->min_bw_5g, reg_info->max_bw_5g);
		   reg_info->min_bw_2ghz, reg_info->max_bw_2ghz,
		   reg_info->min_bw_5ghz, reg_info->max_bw_5ghz);

	ath11k_dbg(ab, ATH11K_DBG_WMI,
		   "%s: num_2g_reg_rules %d num_5g_reg_rules %d", __func__,
		   num_2g_reg_rules, num_5g_reg_rules);
		   "%s: num_2ghz_reg_rules %d num_5ghz_reg_rules %d", __func__,
		   num_2ghz_reg_rules, num_5ghz_reg_rules);

	wmi_reg_rule =
		(struct wmi_regulatory_rule_struct *)((u8 *)chan_list_event_hdr
						+ sizeof(*chan_list_event_hdr)
						+ sizeof(struct wmi_tlv));

	if (num_2g_reg_rules) {
		reg_info->reg_rules_2g_ptr = create_reg_rules_from_wmi(num_2g_reg_rules,
	if (num_2ghz_reg_rules) {
		reg_info->reg_rules_2ghz_ptr =
				create_reg_rules_from_wmi(num_2ghz_reg_rules,
							  wmi_reg_rule);
		if (!reg_info->reg_rules_2g_ptr) {
		if (!reg_info->reg_rules_2ghz_ptr) {
			kfree(tb);
			ath11k_warn(ab, "Unable to Allocate memory for 2g rules\n");
			ath11k_warn(ab, "Unable to Allocate memory for 2 GHz rules\n");
			return -ENOMEM;
		}
	}

	if (num_5g_reg_rules) {
		wmi_reg_rule += num_2g_reg_rules;
		reg_info->reg_rules_5g_ptr = create_reg_rules_from_wmi(num_5g_reg_rules,
	if (num_5ghz_reg_rules) {
		wmi_reg_rule += num_2ghz_reg_rules;
		reg_info->reg_rules_5ghz_ptr =
				create_reg_rules_from_wmi(num_5ghz_reg_rules,
							  wmi_reg_rule);
		if (!reg_info->reg_rules_5g_ptr) {
		if (!reg_info->reg_rules_5ghz_ptr) {
			kfree(tb);
			ath11k_warn(ab, "Unable to Allocate memory for 5g rules\n");
			ath11k_warn(ab, "Unable to Allocate memory for 5 GHz rules\n");
			return -ENOMEM;
		}
	}
@@ -6619,8 +6621,8 @@ static int ath11k_reg_chan_list_event(struct ath11k_base *ab, struct sk_buff *sk
	WARN_ON(1);
mem_free:
	if (reg_info) {
		kfree(reg_info->reg_rules_2g_ptr);
		kfree(reg_info->reg_rules_5g_ptr);
		kfree(reg_info->reg_rules_2ghz_ptr);
		kfree(reg_info->reg_rules_5ghz_ptr);
		kfree(reg_info);
	}
	return ret;
+14 −14
Original line number Diff line number Diff line
@@ -4129,14 +4129,14 @@ struct cur_regulatory_info {
	u8 alpha2[REG_ALPHA2_LEN + 1];
	u32 dfs_region;
	u32 phybitmap;
	u32 min_bw_2g;
	u32 max_bw_2g;
	u32 min_bw_5g;
	u32 max_bw_5g;
	u32 num_2g_reg_rules;
	u32 num_5g_reg_rules;
	struct cur_reg_rule *reg_rules_2g_ptr;
	struct cur_reg_rule *reg_rules_5g_ptr;
	u32 min_bw_2ghz;
	u32 max_bw_2ghz;
	u32 min_bw_5ghz;
	u32 max_bw_5ghz;
	u32 num_2ghz_reg_rules;
	u32 num_5ghz_reg_rules;
	struct cur_reg_rule *reg_rules_2ghz_ptr;
	struct cur_reg_rule *reg_rules_5ghz_ptr;
};

struct wmi_reg_chan_list_cc_event {
@@ -4148,12 +4148,12 @@ struct wmi_reg_chan_list_cc_event {
	u32 domain_code;
	u32 dfs_region;
	u32 phybitmap;
	u32 min_bw_2g;
	u32 max_bw_2g;
	u32 min_bw_5g;
	u32 max_bw_5g;
	u32 num_2g_reg_rules;
	u32 num_5g_reg_rules;
	u32 min_bw_2ghz;
	u32 max_bw_2ghz;
	u32 min_bw_5ghz;
	u32 max_bw_5ghz;
	u32 num_2ghz_reg_rules;
	u32 num_5ghz_reg_rules;
} __packed;

struct wmi_regulatory_rule_struct {