Loading Documentation/devicetree/bindings/spi/spi-controller.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -31,7 +31,7 @@ properties: If that property is used, the number of chip selects will be increased automatically with max(cs-gpios, hardware chip selects). So if, for example, the controller has 2 CS lines, and the So if, for example, the controller has 4 CS lines, and the cs-gpios looks like this cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; Loading drivers/spi/spi-bcm-qspi.c +2 −2 Original line number Diff line number Diff line Loading @@ -343,7 +343,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, { int bpc = 0, bpp = 0; u8 command = op->cmd.opcode; int width = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE; int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; int addrlen = op->addr.nbytes; int flex_mode = 1; Loading Loading @@ -981,7 +981,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem, if (mspi_read) return bcm_qspi_mspi_exec_mem_op(spi, op); ret = bcm_qspi_bspi_set_mode(qspi, op, -1); ret = bcm_qspi_bspi_set_mode(qspi, op, 0); if (!ret) ret = bcm_qspi_bspi_exec_mem_op(spi, op); Loading drivers/spi/spi-bcm2835.c +12 −2 Original line number Diff line number Diff line Loading @@ -319,6 +319,13 @@ static void bcm2835_spi_reset_hw(struct spi_controller *ctlr) BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_DMAEN | BCM2835_SPI_CS_TA); /* * Transmission sometimes breaks unless the DONE bit is written at the * end of every transfer. The spec says it's a RO bit. Either the * spec is wrong and the bit is actually of type RW1C, or it's a * hardware erratum. */ cs |= BCM2835_SPI_CS_DONE; /* and reset RX/TX FIFOS */ cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; Loading Loading @@ -477,7 +484,9 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, bcm2835_wr_fifo_count(bs, bs->rx_prologue); bcm2835_wait_tx_fifo_empty(bs); bcm2835_rd_fifo_count(bs, bs->rx_prologue); bcm2835_spi_reset_hw(ctlr); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX | BCM2835_SPI_CS_DONE); dma_sync_single_for_device(ctlr->dma_rx->device->dev, sg_dma_address(&tfr->rx_sg.sgl[0]), Loading @@ -498,7 +507,8 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, | BCM2835_SPI_CS_DMAEN); bcm2835_wr_fifo_count(bs, tx_remaining); bcm2835_wait_tx_fifo_empty(bs); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX | BCM2835_SPI_CS_DONE); } if (likely(!bs->tx_spillover)) { Loading drivers/spi/spi-dw-pci.c +14 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ struct spi_pci_desc { int (*setup)(struct dw_spi *); u16 num_cs; u16 bus_num; u32 max_freq; }; static struct spi_pci_desc spi_pci_mid_desc_1 = { Loading @@ -33,6 +34,12 @@ static struct spi_pci_desc spi_pci_mid_desc_2 = { .bus_num = 1, }; static struct spi_pci_desc spi_pci_ehl_desc = { .num_cs = 1, .bus_num = -1, .max_freq = 100000000, }; static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct dw_spi *dws; Loading Loading @@ -65,6 +72,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (desc) { dws->num_cs = desc->num_cs; dws->bus_num = desc->bus_num; dws->max_freq = desc->max_freq; if (desc->setup) { ret = desc->setup(dws); Loading Loading @@ -125,8 +133,14 @@ static const struct pci_device_id pci_ids[] = { { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1}, /* Intel MID platform SPI controller 2 */ { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2}, /* Intel Elkhart Lake PSE SPI controllers */ { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc}, {}, }; MODULE_DEVICE_TABLE(pci, pci_ids); static struct pci_driver dw_spi_driver = { .name = DRIVER_NAME, Loading drivers/spi/spi-fsl-dspi.c +3 −1 Original line number Diff line number Diff line Loading @@ -886,11 +886,13 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) trans_mode); } } } return IRQ_HANDLED; } return IRQ_NONE; } static const struct of_device_id fsl_dspi_dt_ids[] = { { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, Loading Loading
Documentation/devicetree/bindings/spi/spi-controller.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -31,7 +31,7 @@ properties: If that property is used, the number of chip selects will be increased automatically with max(cs-gpios, hardware chip selects). So if, for example, the controller has 2 CS lines, and the So if, for example, the controller has 4 CS lines, and the cs-gpios looks like this cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; Loading
drivers/spi/spi-bcm-qspi.c +2 −2 Original line number Diff line number Diff line Loading @@ -343,7 +343,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, { int bpc = 0, bpp = 0; u8 command = op->cmd.opcode; int width = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE; int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; int addrlen = op->addr.nbytes; int flex_mode = 1; Loading Loading @@ -981,7 +981,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem, if (mspi_read) return bcm_qspi_mspi_exec_mem_op(spi, op); ret = bcm_qspi_bspi_set_mode(qspi, op, -1); ret = bcm_qspi_bspi_set_mode(qspi, op, 0); if (!ret) ret = bcm_qspi_bspi_exec_mem_op(spi, op); Loading
drivers/spi/spi-bcm2835.c +12 −2 Original line number Diff line number Diff line Loading @@ -319,6 +319,13 @@ static void bcm2835_spi_reset_hw(struct spi_controller *ctlr) BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_DMAEN | BCM2835_SPI_CS_TA); /* * Transmission sometimes breaks unless the DONE bit is written at the * end of every transfer. The spec says it's a RO bit. Either the * spec is wrong and the bit is actually of type RW1C, or it's a * hardware erratum. */ cs |= BCM2835_SPI_CS_DONE; /* and reset RX/TX FIFOS */ cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; Loading Loading @@ -477,7 +484,9 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, bcm2835_wr_fifo_count(bs, bs->rx_prologue); bcm2835_wait_tx_fifo_empty(bs); bcm2835_rd_fifo_count(bs, bs->rx_prologue); bcm2835_spi_reset_hw(ctlr); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX | BCM2835_SPI_CS_DONE); dma_sync_single_for_device(ctlr->dma_rx->device->dev, sg_dma_address(&tfr->rx_sg.sgl[0]), Loading @@ -498,7 +507,8 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr, | BCM2835_SPI_CS_DMAEN); bcm2835_wr_fifo_count(bs, tx_remaining); bcm2835_wait_tx_fifo_empty(bs); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX); bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX | BCM2835_SPI_CS_DONE); } if (likely(!bs->tx_spillover)) { Loading
drivers/spi/spi-dw-pci.c +14 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ struct spi_pci_desc { int (*setup)(struct dw_spi *); u16 num_cs; u16 bus_num; u32 max_freq; }; static struct spi_pci_desc spi_pci_mid_desc_1 = { Loading @@ -33,6 +34,12 @@ static struct spi_pci_desc spi_pci_mid_desc_2 = { .bus_num = 1, }; static struct spi_pci_desc spi_pci_ehl_desc = { .num_cs = 1, .bus_num = -1, .max_freq = 100000000, }; static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct dw_spi *dws; Loading Loading @@ -65,6 +72,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (desc) { dws->num_cs = desc->num_cs; dws->bus_num = desc->bus_num; dws->max_freq = desc->max_freq; if (desc->setup) { ret = desc->setup(dws); Loading Loading @@ -125,8 +133,14 @@ static const struct pci_device_id pci_ids[] = { { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1}, /* Intel MID platform SPI controller 2 */ { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2}, /* Intel Elkhart Lake PSE SPI controllers */ { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc}, { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc}, {}, }; MODULE_DEVICE_TABLE(pci, pci_ids); static struct pci_driver dw_spi_driver = { .name = DRIVER_NAME, Loading
drivers/spi/spi-fsl-dspi.c +3 −1 Original line number Diff line number Diff line Loading @@ -886,11 +886,13 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) trans_mode); } } } return IRQ_HANDLED; } return IRQ_NONE; } static const struct of_device_id fsl_dspi_dt_ids[] = { { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, Loading