Loading drivers/net/mv643xx_eth.c +4 −17 Original line number Diff line number Diff line Loading @@ -118,37 +118,24 @@ static char mv643xx_driver_version[] = "1.0"; #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ #define RIFB (1 << 0) #define RX_BURST_SIZE_1_64BIT (0 << 1) #define RX_BURST_SIZE_2_64BIT (1 << 1) /* * SDMA configuration register. */ #define RX_BURST_SIZE_4_64BIT (2 << 1) #define RX_BURST_SIZE_8_64BIT (3 << 1) #define RX_BURST_SIZE_16_64BIT (4 << 1) #define BLM_RX_NO_SWAP (1 << 4) #define BLM_RX_BYTE_SWAP (0 << 4) #define BLM_TX_NO_SWAP (1 << 5) #define BLM_TX_BYTE_SWAP (0 << 5) #define DESCRIPTORS_BYTE_SWAP (1 << 6) #define DESCRIPTORS_NO_SWAP (0 << 6) #define IPG_INT_RX(value) (((value) & 0x3fff) << 8) #define TX_BURST_SIZE_1_64BIT (0 << 22) #define TX_BURST_SIZE_2_64BIT (1 << 22) #define TX_BURST_SIZE_4_64BIT (2 << 22) #define TX_BURST_SIZE_8_64BIT (3 << 22) #define TX_BURST_SIZE_16_64BIT (4 << 22) #if defined(__BIG_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ IPG_INT_RX(0) | \ TX_BURST_SIZE_4_64BIT #elif defined(__LITTLE_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ BLM_RX_NO_SWAP | \ BLM_TX_NO_SWAP | \ IPG_INT_RX(0) | \ TX_BURST_SIZE_4_64BIT #else #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined Loading Loading
drivers/net/mv643xx_eth.c +4 −17 Original line number Diff line number Diff line Loading @@ -118,37 +118,24 @@ static char mv643xx_driver_version[] = "1.0"; #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ #define RIFB (1 << 0) #define RX_BURST_SIZE_1_64BIT (0 << 1) #define RX_BURST_SIZE_2_64BIT (1 << 1) /* * SDMA configuration register. */ #define RX_BURST_SIZE_4_64BIT (2 << 1) #define RX_BURST_SIZE_8_64BIT (3 << 1) #define RX_BURST_SIZE_16_64BIT (4 << 1) #define BLM_RX_NO_SWAP (1 << 4) #define BLM_RX_BYTE_SWAP (0 << 4) #define BLM_TX_NO_SWAP (1 << 5) #define BLM_TX_BYTE_SWAP (0 << 5) #define DESCRIPTORS_BYTE_SWAP (1 << 6) #define DESCRIPTORS_NO_SWAP (0 << 6) #define IPG_INT_RX(value) (((value) & 0x3fff) << 8) #define TX_BURST_SIZE_1_64BIT (0 << 22) #define TX_BURST_SIZE_2_64BIT (1 << 22) #define TX_BURST_SIZE_4_64BIT (2 << 22) #define TX_BURST_SIZE_8_64BIT (3 << 22) #define TX_BURST_SIZE_16_64BIT (4 << 22) #if defined(__BIG_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ IPG_INT_RX(0) | \ TX_BURST_SIZE_4_64BIT #elif defined(__LITTLE_ENDIAN) #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ RX_BURST_SIZE_4_64BIT | \ BLM_RX_NO_SWAP | \ BLM_TX_NO_SWAP | \ IPG_INT_RX(0) | \ TX_BURST_SIZE_4_64BIT #else #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined Loading