Unverified Commit 26c350fe authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-dt64-5.20-1' of... 

Merge tag 'mvebu-dt64-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt

mvebu dt64 for 5.20 (part 1)

Add support for Marvell 98DX2530 (and variants)

* tag 'mvebu-dt64-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: marvell: enable the 98DX2530 pinctrl driver
  arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
  dt-bindings: marvell: Document the AC5/AC5X compatibles

Link: https://lore.kernel.org/r/87cze1qlg3.fsf@BL-laptop


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7dbb1b0b 8225663e

Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell Alleycat5/5X Platforms



maintainers:

  - Chris Packham <chris.packham@alliedtelesis.co.nz>



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: Alleycat5 (98DX25xx) Reference Design

        items:

          - enum:

              - marvell,rd-ac5

          - const: marvell,ac5



      - description: Alleycat5X (98DX35xx) Reference Design

        items:

          - enum:

              - marvell,rd-ac5x

          - const: marvell,ac5x

          - const: marvell,ac5



additionalProperties: true



...

arch/arm64/Kconfig.platforms

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@@ -192,11 +192,13 @@ config ARCH_MVEBU 
	select PINCTRL_ARMADA_37XX

	select PINCTRL_ARMADA_AP806

	select PINCTRL_ARMADA_CP110

	select PINCTRL_AC5

	help

	  This enables support for Marvell EBU familly, including:

	   - Armada 3700 SoC Family

	   - Armada 7K SoC Family

	   - Armada 8K SoC Family

	   - 98DX2530 SoC Family



config ARCH_MXC

	bool "ARMv8 based NXP i.MX SoC family"

arch/arm64/boot/dts/marvell/Makefile

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@@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb 
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb

dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb

arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree For AC5.

 *

 * Copyright (C) 2021 Marvell

 * Copyright (C) 2022 Allied Telesis Labs

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	model = "Marvell AC5 SoC";

	compatible = "marvell,ac5";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0>;

				};

				core1 {

					cpu = <&cpu1>;

				};

			};

		};



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a55";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};



		l2: l2-cache {

			compatible = "cache";

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		dma-ranges;



		internal-regs@7f000000 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "simple-bus";

			/* 16M internal register @ 0x7f00_0000 */

			ranges = <0x0 0x0 0x7f000000 0x1000000>;

			dma-coherent;



			uart0: serial@12000 {

				compatible = "snps,dw-apb-uart";

				reg = <0x12000 0x100>;

				reg-shift = <2>;

				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

				reg-io-width = <1>;

				clocks = <&cnm_clock>;

				status = "okay";

			};



			mdio: mdio@22004 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "marvell,orion-mdio";

				reg = <0x22004 0x4>;

				clocks = <&cnm_clock>;

			};



			i2c0: i2c@11000{

				compatible = "marvell,mv78230-i2c";

				reg = <0x11000 0x20>;

				#address-cells = <1>;

				#size-cells = <0>;



				clocks = <&cnm_clock>;

				clock-names = "core";

				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

				clock-frequency=<100000>;



				pinctrl-names = "default", "gpio";

				pinctrl-0 = <&i2c0_pins>;

				pinctrl-1 = <&i2c0_gpio>;

				scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;

				sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;

				status = "disabled";

			};



			i2c1: i2c@11100{

				compatible = "marvell,mv78230-i2c";

				reg = <0x11100 0x20>;

				#address-cells = <1>;

				#size-cells = <0>;



				clocks = <&cnm_clock>;

				clock-names = "core";

				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;

				clock-frequency=<100000>;



				pinctrl-names = "default", "gpio";

				pinctrl-0 = <&i2c1_pins>;

				pinctrl-1 = <&i2c1_gpio>;

				scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;

				sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;

				status = "disabled";

			};



			gpio0: gpio@18100 {

				compatible = "marvell,orion-gpio";

				reg = <0x18100 0x40>;

				ngpios = <32>;

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl0 0 0 32>;

				marvell,pwm-offset = <0x1f0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;

			};



			gpio1: gpio@18140 {

				reg = <0x18140 0x40>;

				compatible = "marvell,orion-gpio";

				ngpios = <14>;

				gpio-controller;

				#gpio-cells = <2>;

				gpio-ranges = <&pinctrl0 0 32 14>;

				marvell,pwm-offset = <0x1f0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		/*

		 * Dedicated section for devices behind 32bit controllers so we

		 * can configure specific DMA mapping for them

		 */

		behind-32bit-controller@7f000000 {

			compatible = "simple-bus";

			#address-cells = <0x2>;

			#size-cells = <0x2>;

			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;

			/* Host phy ram starts at 0x200M */

			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;

			dma-coherent;



			eth0: ethernet@20000 {

				compatible = "marvell,armada-ac5-neta";

				reg = <0x0 0x20000 0x0 0x4000>;

				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&cnm_clock>;

				phy-mode = "sgmii";

				status = "disabled";

			};



			eth1: ethernet@24000 {

				compatible = "marvell,armada-ac5-neta";

				reg = <0x0 0x24000 0x0 0x4000>;

				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&cnm_clock>;

				phy-mode = "sgmii";

				status = "disabled";

			};



			usb0: usb@80000 {

				compatible = "marvell,orion-ehci";

				reg = <0x0 0x80000 0x0 0x500>;

				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};



			usb1: usb@a0000 {

				compatible = "marvell,orion-ehci";

				reg = <0x0 0xa0000 0x0 0x500>;

				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};

		};



		pinctrl0: pinctrl@80020100 {

			compatible = "marvell,ac5-pinctrl";

			reg = <0 0x80020100 0 0x20>;



			i2c0_pins: i2c0-pins {

				marvell,pins = "mpp26", "mpp27";

				marvell,function = "i2c0";

			};



			i2c0_gpio: i2c0-gpio-pins {

				marvell,pins = "mpp26", "mpp27";

				marvell,function = "gpio";

			};



			i2c1_pins: i2c1-pins {

				marvell,pins = "mpp20", "mpp21";

				marvell,function = "i2c1";

			};



			i2c1_gpio: i2c1-gpio-pins {

				marvell,pins = "mpp20", "mpp21";

				marvell,function = "i2c1";

			};

		};



		spi0: spi@805a0000 {

			compatible = "marvell,armada-3700-spi";

			reg = <0x0 0x805a0000 0x0 0x50>;

			#address-cells = <0x1>;

			#size-cells = <0x0>;

			clocks = <&spi_clock>;

			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

			num-cs = <1>;

			status = "disabled";

		};



		spi1: spi@805a8000 {

			compatible = "marvell,armada-3700-spi";

			reg = <0x0 0x805a8000 0x0 0x50>;

			#address-cells = <0x1>;

			#size-cells = <0x0>;

			clocks = <&spi_clock>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

			num-cs = <1>;

			status = "disabled";

		};



		gic: interrupt-controller@80600000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */

			      <0x0 0x80660000 0x0 0x40000>; /* GICR */

			interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	clocks {

		cnm_clock: cnm-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <328000000>;

		};



		spi_clock: spi-clock {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <200000000>;

		};

	};

};

arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree For RD-AC5X.

 *

 * Copyright (C) 2021 Marvell

 * Copyright (C) 2022 Allied Telesis Labs

 */

/*

 * Device Tree file for Marvell Alleycat 5X development board

 * This board file supports the B configuration of the board

 */



/dts-v1/;



#include "ac5-98dx35xx.dtsi"



/ {

	model = "Marvell RD-AC5X Board";

	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";



	aliases {

		serial0 = &uart0;

		spiflash0 = &spiflash0;

		gpio0 = &gpio0;

		gpio1 = &gpio1;

		ethernet0 = &eth0;

		ethernet1 = &eth1;

	};



	memory@0 {

		device_type = "memory";

		reg = <0x2 0x00000000 0x0 0x40000000>;

	};



	usb1phy: usb-phy {

		compatible = "usb-nop-xceiv";

		#phy-cells = <0>;

	};

};



&mdio {

	phy0: ethernet-phy@0 {

		reg = <0>;

	};

};



&i2c0 {

	status = "okay";

};



&i2c1 {

	status = "okay";

};



&eth0 {

	status = "okay";

	phy-handle = <&phy0>;

};



/* USB0 is a host USB */

&usb0 {

	status = "okay";

};



/* USB1 is a peripheral USB */

&usb1 {

	status = "okay";

	phys = <&usb1phy>;

	phy-names = "usb-phy";

	dr_mode = "peripheral";

};



&spi0 {

	status = "okay";



	spiflash0: flash@0 {

		compatible = "jedec,spi-nor";

		spi-max-frequency = <50000000>;

		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */

		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */

		reg = <0>;



		#address-cells = <1>;

		#size-cells = <1>;



		partition@0 {

			label = "spi_flash_part0";

			reg = <0x0 0x800000>;

		};



		parition@1 {

			label = "spi_flash_part1";

			reg = <0x800000 0x700000>;

		};



		parition@2 {

			label = "spi_flash_part2";

			reg = <0xF00000 0x100000>;

		};

	};

};