Commit 27493cb8 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load 



Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
platforms that supports DMC, not only for geminilake and broxton.

While at is also taking the oportunity to simply the code.

BSpec: 7402
BSpec: 49436
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-1-jose.souza@intel.com
parent 3d1adc3d

drivers/gpu/drm/i915/display/intel_dmc.c

+3 −13
Original line number Diff line number Diff line
@@ -255,21 +255,11 @@ intel_get_stepping_info(struct drm_i915_private *i915, 


static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)

{

	u32 val, mask;



	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;



	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		mask |= DC_STATE_DEBUG_MASK_CORES;



	/* The below bit doesn't need to be cleared ever afterwards */

	val = intel_de_read(dev_priv, DC_STATE_DEBUG);

	if ((val & mask) != mask) {

		val |= mask;

		intel_de_write(dev_priv, DC_STATE_DEBUG, val);

	intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,

		     DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);

	intel_de_posting_read(dev_priv, DC_STATE_DEBUG);

}

}



/**

 * intel_dmc_load_program() - write the firmware from memory to register.