Commit 2782403c authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update metrics for Jaketown 

Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are still at version 20:
    https://download.01.org/perfmon/JKT
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf



Tested:

Not tested on a Jaketown, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...

Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-18-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 70d90a6a

tools/perf/pmu-events/arch/x86/jaketown/cache.json

+779 −803

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/jaketown/floating-point.json

+80 −80
Original line number Diff line number Diff line 
[

    {

        "EventCode": "0xC1",

        "BriefDescription": "Cycles with any input/output SSE or FP assist.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "OTHER_ASSISTS.AVX_STORE",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1e"

    },

    {

        "EventCode": "0xC1",

        "BriefDescription": "Number of SIMD FP assists due to input values.",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x10"

    },

    {

        "EventCode": "0xC1",

        "BriefDescription": "Number of SIMD FP assists due to Output values.",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of X87 assists due to output value.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "EventCode": "0xCA",

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of X87 assists due to input value.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "EventCode": "0xCA",

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of SIMD FP assists due to Output values.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xCA",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of SIMD FP assists due to input values.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "EventCode": "0x10",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "FP_COMP_OPS_EXE.X87",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x40"

    },

    {

        "EventCode": "0x10",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x80"

    },

    {

        "EventCode": "0x10",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x20"

    },

    {

        "EventCode": "0x10",

        "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",

        "Counter": "0,1,2,3",

        "UMask": "0x40",

        "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x10",

        "EventName": "FP_COMP_OPS_EXE.X87",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "EventCode": "0x10",

        "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",

        "Counter": "0,1,2,3",

        "UMask": "0x80",

        "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_STORE",

        "SampleAfterValue": "100003",

        "UMask": "0x8"

    },

    {

        "EventCode": "0x11",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "SIMD_FP_256.PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",

        "UMask": "0x10"

    },

    {

        "EventCode": "0x11",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xCA",

        "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",

        "Counter": "0,1,2,3",

        "UMask": "0x1e",

        "EventName": "FP_ASSIST.ANY",

        "SampleAfterValue": "100003",

        "BriefDescription": "Cycles with any input/output SSE or FP assist.",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x11",

        "EventName": "SIMD_FP_256.PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "UMask": "0x1"

    }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/jaketown/frontend.json

+186 −177

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json

+80 −60

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/jaketown/memory.json

+239 −239

File changed.

Preview size limit exceeded, changes collapsed.