Commit 28aa30b0 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: Fix planar formats on Tegra186 and later 



Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV
register's PITCH_U field to ensure the correct value is used in all
cases. This isn't currently causing any problems because the pitch
for both U and V planes is always the same.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 025c6643

drivers/gpu/drm/tegra/hub.c

+1 −1
Original line number Diff line number Diff line
@@ -673,7 +673,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, 
		tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);

		tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);



		value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]);

		value = PITCH_U(fb->pitches[1]) | PITCH_V(fb->pitches[2]);

		tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);

	} else {

		tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U);