Commit 2928de97 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Fixes-applied-to-VCS8514' 



Bjarni Jonasson says:

====================
Fixes applied to VCS8514

3 different fixes applied to VSC8514:
LCPLL reset, serdes calibration and coma mode disabled.
Especially the serdes calibration is large and is now placed
in a new file 'mscc_serdes.c' which can act as
a placeholder for future serdes configuration.

v1 -> v2:
  Preserved reversed christmas tree
  Removed forward definitions
  Fixed build issues
  Changed net to net-next

v2 -> v3:
  Added cover letter.
  Removed ena_clk_bypass from function call
  Created mscc_serdes.c and .h for serdes configuration
  Modified coma register config.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 455843d2 ca0d7fd0

drivers/net/phy/mscc/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 


obj-$(CONFIG_MICROSEMI_PHY) := mscc.o

mscc-objs := mscc_main.o

mscc-objs += mscc_serdes.o



ifdef CONFIG_MACSEC

mscc-objs += mscc_macsec.o

drivers/net/phy/mscc/mscc.h

+28 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ enum rgmii_clock_delay { 
#define PHY_MCB_S6G_READ		  BIT(30)



#define PHY_S6G_PLL5G_CFG0		  0x06

#define PHY_S6G_PLL5G_CFG2		  0x08

#define PHY_S6G_LCPLL_CFG		  0x11

#define PHY_S6G_PLL_CFG			  0x2b

#define PHY_S6G_COMMON_CFG		  0x2c
@@ -121,6 +122,9 @@ enum rgmii_clock_delay { 
#define PHY_S6G_PLL_FSM_CTRL_DATA_POS	  8

#define PHY_S6G_PLL_FSM_ENA_POS		  7



#define PHY_S6G_CFG2_FSM_DIS              1

#define PHY_S6G_CFG2_FSM_CLK_BP          23



#define MSCC_EXT_PAGE_ACCESS		  31

#define MSCC_PHY_PAGE_STANDARD		  0x0000 /* Standard registers */

#define MSCC_PHY_PAGE_EXTENDED		  0x0001 /* Extended registers */
@@ -136,6 +140,10 @@ enum rgmii_clock_delay { 
#define MSCC_PHY_PAGE_1588		  0x1588 /* PTP (1588) */

#define MSCC_PHY_PAGE_TEST		  0x2a30 /* Test reg */

#define MSCC_PHY_PAGE_TR		  0x52b5 /* Token ring registers */

#define MSCC_PHY_GPIO_CONTROL_2           14



#define MSCC_PHY_COMA_MODE		  0x2000 /* input(1) / output(0) */

#define MSCC_PHY_COMA_OUTPUT		  0x1000 /* value to output */



/* Extended Page 1 Registers */

#define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT	  18
@@ -335,6 +343,10 @@ enum rgmii_clock_delay { 
#define VSC8584_REVB				0x0001

#define MSCC_DEV_REV_MASK			GENMASK(3, 0)



#define MSCC_ROM_TRAP_SERDES_6G_CFG		0x1E48

#define MSCC_RAM_TRAP_SERDES_6G_CFG		0x1E4F

#define PATCH_VEC_ZERO_EN			0x0100



struct reg_val {

	u16	reg;

	u32	val;
@@ -412,6 +424,22 @@ struct vsc8531_edge_rate_table { 
};

#endif /* CONFIG_OF_MDIO */



enum csr_target {

	MACRO_CTRL  = 0x07,

};



u32 vsc85xx_csr_read(struct phy_device *phydev,

		     enum csr_target target, u32 reg);



int vsc85xx_csr_write(struct phy_device *phydev,

		      enum csr_target target, u32 reg, u32 val);



int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val);

int phy_base_read(struct phy_device *phydev, u32 regnum);

int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);

int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);

int vsc8584_cmd(struct phy_device *phydev, u16 val);



#if IS_ENABLED(CONFIG_MACSEC)

int vsc8584_macsec_init(struct phy_device *phydev);

void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);

drivers/net/phy/mscc/mscc_main.c

+353 −255

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/phy/mscc/mscc_serdes.c

0 → 100644
+650 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/phy/mscc/mscc_serdes.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/*

 * Driver for Microsemi VSC85xx PHYs

 *

 * Copyright (c) 2021 Microsemi Corporation

 */



#ifndef _MSCC_SERDES_PHY_H_

#define _MSCC_SERDES_PHY_H_



#define PHY_S6G_PLL5G_CFG2_GAIN_MASK      GENMASK(9, 5)

#define PHY_S6G_PLL5G_CFG2_ENA_GAIN       1



#define PHY_S6G_DES_PHY_CTRL_POS	  13

#define PHY_S6G_DES_MBTR_CTRL_POS	  10

#define PHY_S6G_DES_CPMD_SEL_POS	  8

#define PHY_S6G_DES_BW_HYST_POS		  5

#define PHY_S6G_DES_BW_ANA_POS		  1

#define PHY_S6G_DES_CFG			  0x21

#define PHY_S6G_IB_CFG0			  0x22

#define PHY_S6G_IB_CFG1			  0x23

#define PHY_S6G_IB_CFG2			  0x24

#define PHY_S6G_IB_CFG3			  0x25

#define PHY_S6G_IB_CFG4			  0x26

#define PHY_S6G_GP_CFG			  0x2E

#define PHY_S6G_DFT_CFG0		  0x35

#define PHY_S6G_IB_DFT_CFG2		  0x37



int vsc85xx_sd6g_config_v2(struct phy_device *phydev);



#endif /* _MSCC_PHY_SERDES_H_ */