Unverified Commit 2981deb8 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: PolarFire SoC Device Tree Updates 

This add a device tree for Sundance Polarberry, along with various
cleanups to the PolarFire SOC device trees and bindings.

Link: https://lore.kernel.org/r/20220509142610.128590-1-conor.dooley@microchip.com

* 'riscv-pfsoc-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
  riscv: dts: icicle: sort nodes alphabetically
  riscv: microchip: icicle: readability fixes
  riscv: dts: microchip: add the sundance polarberry
  dt-bindings: riscv: microchip: add polarberry compatible string
  dt-bindings: vendor-prefixes: add Sundance DSP
  riscv: dts: microchip: make the fabric dtsi board specific
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: remove soc vendor from filenames
  riscv: dts: microchip: move sysctrlr out of soc bus
  riscv: dts: microchip: remove icicle memory clocks
parents 35b51afd df403b7c

Documentation/devicetree/bindings/riscv/microchip.yaml

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ properties: 
    items:

      - enum:

          - microchip,mpfs-icicle-kit

          - microchip,mpfs-icicle-reference-rtlv2203

          - sundance,polarberry

      - const: microchip,mpfs



additionalProperties: true

Documentation/devicetree/bindings/vendor-prefixes.yaml

+2 −0
Original line number Diff line number Diff line
@@ -1207,6 +1207,8 @@ patternProperties: 
    description: Summit microelectronics

  "^sunchip,.*":

    description: Shenzhen Sunchip Technology Co., Ltd

  "^sundance,.*":

    description: Sundance DSP Inc.

  "^sunplus,.*":

    description: Sunplus Technology Co., Ltd.

  "^SUNW,.*":

arch/riscv/boot/dts/microchip/Makefile

+2 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb

obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi→arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 
/* Copyright (c) 2020-2021 Microchip Technology Inc */



/ {

	compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";



	core_pwm0: pwm@41000000 {

		compatible = "microchip,corepwm-rtl-v4";

		reg = <0x0 0x41000000 0x0 0xF0>;

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts→arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+53 −52
Original line number Diff line number Diff line
@@ -3,7 +3,8 @@ 


/dts-v1/;



#include "microchip-mpfs.dtsi"

#include "mpfs.dtsi"

#include "mpfs-icicle-kit-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define RTCCLK_FREQ		1000000
@@ -32,41 +33,71 @@ cpus { 
	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x2e000000>;

		clocks = <&clkcfg CLK_DDRC>;

		status = "okay";

	};



	ddrc_cache_hi: memory@1000000000 {

		device_type = "memory";

		reg = <0x10 0x0 0x0 0x40000000>;

		clocks = <&clkcfg CLK_DDRC>;

		status = "okay";

	};

};



&refclk {

	clock-frequency = <125000000>;

&core_pwm0 {

	status = "okay";

};



&mmuart1 {

&gpio2 {

	interrupts = <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>;

	status = "okay";

};



&mmuart2 {

&i2c0 {

	status = "okay";

};



&mmuart3 {

&i2c1 {

	status = "okay";

};



&mmuart4 {

&i2c2 {

	status = "okay";

};



&mmc {

&mac0 {

	phy-mode = "sgmii";

	phy-handle = <&phy0>;

	status = "okay";

};



&mac1 {

	phy-mode = "sgmii";

	phy-handle = <&phy1>;

	status = "okay";



	phy1: ethernet-phy@9 {

		reg = <9>;

		ti,fifo-depth = <0x1>;

	};



	phy0: ethernet-phy@8 {

		reg = <8>;

		ti,fifo-depth = <0x1>;

	};

};



&mbox {

	status = "okay";

};



&mmc {

	bus-width = <4>;

	disable-wp;

	cap-sd-highspeed;
@@ -78,73 +109,46 @@ &mmc { 
	sd-uhs-sdr25;

	sd-uhs-sdr50;

	sd-uhs-sdr104;

};



&spi0 {

	status = "okay";

};



&spi1 {

&mmuart1 {

	status = "okay";

};



&qspi {

&mmuart2 {

	status = "okay";

};



&i2c0 {

&mmuart3 {

	status = "okay";

};



&i2c1 {

&mmuart4 {

	status = "okay";

};



&i2c2 {

&pcie {

	status = "okay";

};



&mac0 {

	phy-mode = "sgmii";

	phy-handle = <&phy0>;

};



&mac1 {

&qspi {

	status = "okay";

	phy-mode = "sgmii";

	phy-handle = <&phy1>;

	phy1: ethernet-phy@9 {

		reg = <9>;

		ti,fifo-depth = <0x1>;

	};

	phy0: ethernet-phy@8 {

		reg = <8>;

		ti,fifo-depth = <0x1>;

	};

};



&gpio2 {

	interrupts = <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>,

		     <53>, <53>, <53>, <53>;

	status = "okay";

&refclk {

	clock-frequency = <125000000>;

};



&rtc {

	status = "okay";

};



&usb {

&spi0 {

	status = "okay";

	dr_mode = "host";

};



&mbox {

&spi1 {

	status = "okay";

};
@@ -152,10 +156,7 @@ &syscontroller { 
	status = "okay";

};



&pcie {

	status = "okay";

};



&core_pwm0 {

&usb {

	status = "okay";

	dr_mode = "host";

};