Unverified Commit 2a03c600 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Arnd Bergmann
Browse files

ARM: dts: uniphier: Align node names for SoC-dependent controller and PHYs with bindings 



The node names for SoC-dependent controllers and PHYs should be
generic ones according to the DT schemas.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20230207023514.29783-2-hayashi.kunihiko@socionext.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 153927e6

arch/arm/boot/dts/uniphier-ld4.dtsi

+11 −11
Original line number Diff line number Diff line
@@ -207,33 +207,33 @@ smpctrl@59801000 { 
			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

		syscon@59810000 {

			compatible = "socionext,uniphier-ld4-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

			mio_clk: clock-controller {

				compatible = "socionext,uniphier-ld4-mio-clock";

				#clock-cells = <1>;

			};



			mio_rst: reset {

			mio_rst: reset-controller {

				compatible = "socionext,uniphier-ld4-mio-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

		syscon@59820000 {

			compatible = "socionext,uniphier-ld4-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

			peri_clk: clock-controller {

				compatible = "socionext,uniphier-ld4-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

			peri_rst: reset-controller {

				compatible = "socionext,uniphier-ld4-peri-reset";

				#reset-cells = <1>;

			};
@@ -334,7 +334,7 @@ usb2: usb@5a820100 { 
			has-transaction-translator;

		};



		soc-glue@5f800000 {

		syscon@5f800000 {

			compatible = "socionext,uniphier-ld4-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -344,7 +344,7 @@ pinctrl: pinctrl { 
			};

		};



		soc-glue@5f900000 {

		syscon@5f900000 {

			compatible = "socionext,uniphier-ld4-soc-glue-debug",

				     "simple-mfd";

			#address-cells = <1>;
@@ -393,17 +393,17 @@ aidet: interrupt-controller@61830000 { 
			#interrupt-cells = <2>;

		};



		sysctrl@61840000 {

		syscon@61840000 {

			compatible = "socionext,uniphier-ld4-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

			sys_clk: clock-controller {

				compatible = "socionext,uniphier-ld4-clock";

				#clock-cells = <1>;

			};



			sys_rst: reset {

			sys_rst: reset-controller {

				compatible = "socionext,uniphier-ld4-reset";

				#reset-cells = <1>;

			};

arch/arm/boot/dts/uniphier-pro4.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -241,33 +241,33 @@ smpctrl@59801000 { 
			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

		syscon@59810000 {

			compatible = "socionext,uniphier-pro4-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

			mio_clk: clock-controller {

				compatible = "socionext,uniphier-pro4-mio-clock";

				#clock-cells = <1>;

			};



			mio_rst: reset {

			mio_rst: reset-controller {

				compatible = "socionext,uniphier-pro4-mio-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

		syscon@59820000 {

			compatible = "socionext,uniphier-pro4-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

			peri_clk: clock-controller {

				compatible = "socionext,uniphier-pro4-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

			peri_rst: reset-controller {

				compatible = "socionext,uniphier-pro4-peri-reset";

				#reset-cells = <1>;

			};
@@ -375,7 +375,7 @@ usb3: usb@5a810100 { 
			has-transaction-translator;

		};



		soc_glue: soc-glue@5f800000 {

		soc_glue: syscon@5f800000 {

			compatible = "socionext,uniphier-pro4-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -384,7 +384,7 @@ pinctrl: pinctrl { 
				compatible = "socionext,uniphier-pro4-pinctrl";

			};



			usb-controller {

			usb-hub {

				compatible = "socionext,uniphier-pro4-usb2-phy";

				#address-cells = <1>;

				#size-cells = <0>;
@@ -412,13 +412,13 @@ usb_phy3: phy@3 { 
				};

			};



			sg_clk: clock {

			sg_clk: clock-controller {

				compatible = "socionext,uniphier-pro4-sg-clock";

				#clock-cells = <1>;

			};

		};



		soc-glue@5f900000 {

		syscon@5f900000 {

			compatible = "socionext,uniphier-pro4-soc-glue-debug",

				     "simple-mfd";

			#address-cells = <1>;
@@ -480,17 +480,17 @@ intc: interrupt-controller@60001000 { 
			interrupt-controller;

		};



		sysctrl@61840000 {

		syscon@61840000 {

			compatible = "socionext,uniphier-pro4-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

			sys_clk: clock-controller {

				compatible = "socionext,uniphier-pro4-clock";

				#clock-cells = <1>;

			};



			sys_rst: reset {

			sys_rst: reset-controller {

				compatible = "socionext,uniphier-pro4-reset";

				#reset-cells = <1>;

			};
@@ -549,7 +549,7 @@ ahci0_rst: reset-controller@0 { 
				#reset-cells = <1>;

			};



			ahci0_phy: sata-phy@10 {

			ahci0_phy: phy@10 {

				compatible = "socionext,uniphier-pro4-ahci-phy";

				reg = <0x10 0x40>;

				clock-names = "link", "gio";
@@ -595,7 +595,7 @@ ahci1_rst: reset-controller@0 { 
				#reset-cells = <1>;

			};



			ahci1_phy: sata-phy@10 {

			ahci1_phy: phy@10 {

				compatible = "socionext,uniphier-pro4-ahci-phy";

				reg = <0x10 0x40>;

				clock-names = "link", "gio";
@@ -642,7 +642,7 @@ usb0_vbus: regulator@0 { 
				resets = <&sys_rst 12>, <&sys_rst 14>;

			};



			usb0_ssphy: ss-phy@10 {

			usb0_ssphy: phy@10 {

				compatible = "socionext,uniphier-pro4-usb3-ssphy";

				reg = <0x10 0x10>;

				#phy-cells = <0>;
@@ -653,7 +653,7 @@ usb0_ssphy: ss-phy@10 { 
				vbus-supply = <&usb0_vbus>;

			};



			usb0_rst: reset@40 {

			usb0_rst: reset-controller@40 {

				compatible = "socionext,uniphier-pro4-usb3-reset";

				reg = <0x40 0x4>;

				#reset-cells = <1>;
@@ -696,7 +696,7 @@ usb1_vbus: regulator@0 { 
				resets = <&sys_rst 12>, <&sys_rst 15>;

			};



			usb1_rst: reset@40 {

			usb1_rst: reset-controller@40 {

				compatible = "socionext,uniphier-pro4-usb3-reset";

				reg = <0x40 0x4>;

				#reset-cells = <1>;

arch/arm/boot/dts/uniphier-pro5.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -341,39 +341,39 @@ smpctrl@59801000 { 
			reg = <0x59801000 0x400>;

		};



		sdctrl@59810000 {

		syscon@59810000 {

			compatible = "socionext,uniphier-pro5-sdctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x400>;



			sd_clk: clock {

			sd_clk: clock-controller {

				compatible = "socionext,uniphier-pro5-sd-clock";

				#clock-cells = <1>;

			};



			sd_rst: reset {

			sd_rst: reset-controller {

				compatible = "socionext,uniphier-pro5-sd-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

		syscon@59820000 {

			compatible = "socionext,uniphier-pro5-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

			peri_clk: clock-controller {

				compatible = "socionext,uniphier-pro5-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

			peri_rst: reset-controller {

				compatible = "socionext,uniphier-pro5-peri-reset";

				#reset-cells = <1>;

			};

		};



		soc-glue@5f800000 {

		syscon@5f800000 {

			compatible = "socionext,uniphier-pro5-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -383,7 +383,7 @@ pinctrl: pinctrl { 
			};

		};



		soc-glue@5f900000 {

		syscon@5f900000 {

			compatible = "socionext,uniphier-pro5-soc-glue-debug",

				     "simple-mfd";

			#address-cells = <1>;
@@ -455,17 +455,17 @@ intc: interrupt-controller@60001000 { 
			interrupt-controller;

		};



		sysctrl@61840000 {

		syscon@61840000 {

			compatible = "socionext,uniphier-pro5-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

			sys_clk: clock-controller {

				compatible = "socionext,uniphier-pro5-clock";

				#clock-cells = <1>;

			};



			sys_rst: reset {

			sys_rst: reset-controller {

				compatible = "socionext,uniphier-pro5-reset";

				#reset-cells = <1>;

			};
@@ -493,7 +493,7 @@ usb-controller@65b00000 { 
			#size-cells = <1>;

			ranges = <0 0x65b00000 0x400>;



			usb0_rst: reset@0 {

			usb0_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pro5-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;
@@ -512,7 +512,7 @@ usb0_vbus0: regulator@100 { 
				resets = <&sys_rst 12>, <&sys_rst 14>;

			};



			usb0_hsphy0: hs-phy@280 {

			usb0_hsphy0: phy@280 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x280 0x10>;

				#phy-cells = <0>;
@@ -523,7 +523,7 @@ usb0_hsphy0: hs-phy@280 { 
				vbus-supply = <&usb0_vbus0>;

			};



			usb0_ssphy0: ss-phy@380 {

			usb0_ssphy0: phy@380 {

				compatible = "socionext,uniphier-pro5-usb3-ssphy";

				reg = <0x380 0x10>;

				#phy-cells = <0>;
@@ -557,7 +557,7 @@ usb-controller@65d00000 { 
			#size-cells = <1>;

			ranges = <0 0x65d00000 0x400>;



			usb1_rst: reset@0 {

			usb1_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pro5-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;
@@ -585,7 +585,7 @@ usb1_vbus1: regulator@110 { 
				resets = <&sys_rst 12>, <&sys_rst 15>;

			};



			usb1_hsphy0: hs-phy@280 {

			usb1_hsphy0: phy@280 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x280 0x10>;

				#phy-cells = <0>;
@@ -596,7 +596,7 @@ usb1_hsphy0: hs-phy@280 { 
				vbus-supply = <&usb1_vbus0>;

			};



			usb1_hsphy1: hs-phy@290 {

			usb1_hsphy1: phy@290 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x290 0x10>;

				#phy-cells = <0>;
@@ -607,7 +607,7 @@ usb1_hsphy1: hs-phy@290 { 
				vbus-supply = <&usb1_vbus1>;

			};



			usb1_ssphy0: ss-phy@380 {

			usb1_ssphy0: phy@380 {

				compatible = "socionext,uniphier-pro5-usb3-ssphy";

				reg = <0x380 0x10>;

				#phy-cells = <0>;

arch/arm/boot/dts/uniphier-pxs2.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -422,33 +422,33 @@ smpctrl@59801000 { 
			reg = <0x59801000 0x400>;

		};



		sdctrl@59810000 {

		syscon@59810000 {

			compatible = "socionext,uniphier-pxs2-sdctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x400>;



			sd_clk: clock {

			sd_clk: clock-controller {

				compatible = "socionext,uniphier-pxs2-sd-clock";

				#clock-cells = <1>;

			};



			sd_rst: reset {

			sd_rst: reset-controller {

				compatible = "socionext,uniphier-pxs2-sd-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

		syscon@59820000 {

			compatible = "socionext,uniphier-pxs2-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

			peri_clk: clock-controller {

				compatible = "socionext,uniphier-pxs2-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

			peri_rst: reset-controller {

				compatible = "socionext,uniphier-pxs2-peri-reset";

				#reset-cells = <1>;

			};
@@ -488,7 +488,7 @@ sd: mmc@5a400000 { 
			sd-uhs-sdr50;

		};



		soc_glue: soc-glue@5f800000 {

		soc_glue: syscon@5f800000 {

			compatible = "socionext,uniphier-pxs2-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -498,7 +498,7 @@ pinctrl: pinctrl { 
			};

		};



		soc-glue@5f900000 {

		syscon@5f900000 {

			compatible = "socionext,uniphier-pxs2-soc-glue-debug",

				     "simple-mfd";

			#address-cells = <1>;
@@ -555,17 +555,17 @@ intc: interrupt-controller@60001000 { 
			interrupt-controller;

		};



		sysctrl@61840000 {

		syscon@61840000 {

			compatible = "socionext,uniphier-pxs2-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

			sys_clk: clock-controller {

				compatible = "socionext,uniphier-pxs2-clock";

				#clock-cells = <1>;

			};



			sys_rst: reset {

			sys_rst: reset-controller {

				compatible = "socionext,uniphier-pxs2-reset";

				#reset-cells = <1>;

			};
@@ -628,7 +628,7 @@ ahci_rst: reset-controller@0 { 
				#reset-cells = <1>;

			};



			ahci_phy: sata-phy@10 {

			ahci_phy: phy@10 {

				compatible = "socionext,uniphier-pxs2-ahci-phy";

				reg = <0x10 0x10>;

				clock-names = "link";
@@ -662,7 +662,7 @@ usb-controller@65b00000 { 
			#size-cells = <1>;

			ranges = <0 0x65b00000 0x400>;



			usb0_rst: reset@0 {

			usb0_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pxs2-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;
@@ -690,7 +690,7 @@ usb0_vbus1: regulator@110 { 
				resets = <&sys_rst 14>;

			};



			usb0_hsphy0: hs-phy@200 {

			usb0_hsphy0: phy@200 {

				compatible = "socionext,uniphier-pxs2-usb3-hsphy";

				reg = <0x200 0x10>;

				#phy-cells = <0>;
@@ -701,7 +701,7 @@ usb0_hsphy0: hs-phy@200 { 
				vbus-supply = <&usb0_vbus0>;

			};



			usb0_hsphy1: hs-phy@210 {

			usb0_hsphy1: phy@210 {

				compatible = "socionext,uniphier-pxs2-usb3-hsphy";

				reg = <0x210 0x10>;

				#phy-cells = <0>;
@@ -712,7 +712,7 @@ usb0_hsphy1: hs-phy@210 { 
				vbus-supply = <&usb0_vbus1>;

			};



			usb0_ssphy0: ss-phy@300 {

			usb0_ssphy0: phy@300 {

				compatible = "socionext,uniphier-pxs2-usb3-ssphy";

				reg = <0x300 0x10>;

				#phy-cells = <0>;
@@ -723,7 +723,7 @@ usb0_ssphy0: ss-phy@300 { 
				vbus-supply = <&usb0_vbus0>;

			};



			usb0_ssphy1: ss-phy@310 {

			usb0_ssphy1: phy@310 {

				compatible = "socionext,uniphier-pxs2-usb3-ssphy";

				reg = <0x310 0x10>;

				#phy-cells = <0>;
@@ -757,7 +757,7 @@ usb-controller@65d00000 { 
			#size-cells = <1>;

			ranges = <0 0x65d00000 0x400>;



			usb1_rst: reset@0 {

			usb1_rst: reset-controller@0 {

				compatible = "socionext,uniphier-pxs2-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;
@@ -785,7 +785,7 @@ usb1_vbus1: regulator@110 { 
				resets = <&sys_rst 15>;

			};



			usb1_hsphy0: hs-phy@200 {

			usb1_hsphy0: phy@200 {

				compatible = "socionext,uniphier-pxs2-usb3-hsphy";

				reg = <0x200 0x10>;

				#phy-cells = <0>;
@@ -796,7 +796,7 @@ usb1_hsphy0: hs-phy@200 { 
				vbus-supply = <&usb1_vbus0>;

			};



			usb1_hsphy1: hs-phy@210 {

			usb1_hsphy1: phy@210 {

				compatible = "socionext,uniphier-pxs2-usb3-hsphy";

				reg = <0x210 0x10>;

				#phy-cells = <0>;
@@ -807,7 +807,7 @@ usb1_hsphy1: hs-phy@210 { 
				vbus-supply = <&usb1_vbus1>;

			};



			usb1_ssphy0: ss-phy@300 {

			usb1_ssphy0: phy@300 {

				compatible = "socionext,uniphier-pxs2-usb3-ssphy";

				reg = <0x300 0x10>;

				#phy-cells = <0>;

arch/arm/boot/dts/uniphier-sld8.dtsi

+11 −11
Original line number Diff line number Diff line
@@ -211,33 +211,33 @@ smpctrl@59801000 { 
			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

		syscon@59810000 {

			compatible = "socionext,uniphier-sld8-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

			mio_clk: clock-controller {

				compatible = "socionext,uniphier-sld8-mio-clock";

				#clock-cells = <1>;

			};



			mio_rst: reset {

			mio_rst: reset-controller {

				compatible = "socionext,uniphier-sld8-mio-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

		syscon@59820000 {

			compatible = "socionext,uniphier-sld8-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

			peri_clk: clock-controller {

				compatible = "socionext,uniphier-sld8-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

			peri_rst: reset-controller {

				compatible = "socionext,uniphier-sld8-peri-reset";

				#reset-cells = <1>;

			};
@@ -338,7 +338,7 @@ usb2: usb@5a820100 { 
			has-transaction-translator;

		};



		soc-glue@5f800000 {

		syscon@5f800000 {

			compatible = "socionext,uniphier-sld8-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -348,7 +348,7 @@ pinctrl: pinctrl { 
			};

		};



		soc-glue@5f900000 {

		syscon@5f900000 {

			compatible = "socionext,uniphier-sld8-soc-glue-debug",

				     "simple-mfd";

			#address-cells = <1>;
@@ -397,17 +397,17 @@ aidet: interrupt-controller@61830000 { 
			#interrupt-cells = <2>;

		};



		sysctrl@61840000 {

		syscon@61840000 {

			compatible = "socionext,uniphier-sld8-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

			sys_clk: clock-controller {

				compatible = "socionext,uniphier-sld8-clock";

				#clock-cells = <1>;

			};



			sys_rst: reset {

			sys_rst: reset-controller {

				compatible = "socionext,uniphier-sld8-reset";

				#reset-cells = <1>;

			};