Unverified Commit 2b60d727 authored by Mark Brown's avatar Mark Brown
Browse files

Merge branch 'for-5.4' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.5

parents d6b71dfa f6910679

drivers/spi/spi-fsl-lpspi.c

+1 −1
Original line number Diff line number Diff line
@@ -938,7 +938,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev) 
	ret = pm_runtime_get_sync(fsl_lpspi->dev);

	if (ret < 0) {

		dev_err(fsl_lpspi->dev, "failed to enable clock\n");

		return ret;

		goto out_controller_put;

	}



	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);

drivers/spi/spi-fsl-qspi.c

+33 −5
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ 
#define QUADSPI_IPCR			0x08

#define QUADSPI_IPCR_SEQID(x)		((x) << 24)



#define QUADSPI_FLSHCR			0x0c

#define QUADSPI_FLSHCR_TCSS_MASK	GENMASK(3, 0)

#define QUADSPI_FLSHCR_TCSH_MASK	GENMASK(11, 8)

#define QUADSPI_FLSHCR_TDH_MASK		GENMASK(17, 16)



#define QUADSPI_BUF0CR                  0x10

#define QUADSPI_BUF1CR                  0x14

#define QUADSPI_BUF2CR                  0x18
@@ -100,6 +105,9 @@ 
#define QUADSPI_FR			0x160

#define QUADSPI_FR_TFF_MASK		BIT(0)



#define QUADSPI_RSER			0x164

#define QUADSPI_RSER_TFIE		BIT(0)



#define QUADSPI_SPTRCLR			0x16c

#define QUADSPI_SPTRCLR_IPPTRC		BIT(8)

#define QUADSPI_SPTRCLR_BFPTRC		BIT(0)
@@ -117,9 +125,6 @@ 
#define QUADSPI_LCKER_LOCK		BIT(0)

#define QUADSPI_LCKER_UNLOCK		BIT(1)



#define QUADSPI_RSER			0x164

#define QUADSPI_RSER_TFIE		BIT(0)



#define QUADSPI_LUT_BASE		0x310

#define QUADSPI_LUT_OFFSET		(SEQID_LUT * 4 * 4)

#define QUADSPI_LUT_REG(idx) \
@@ -186,6 +191,12 @@ 
 */

#define QUADSPI_QUIRK_BASE_INTERNAL	BIT(4)



/*

 * Controller uses TDH bits in register QUADSPI_FLSHCR.

 * They need to be set in accordance with the DDR/SDR mode.

 */

#define QUADSPI_QUIRK_USE_TDH_SETTING	BIT(5)



struct fsl_qspi_devtype_data {

	unsigned int rxfifo;

	unsigned int txfifo;
@@ -218,7 +229,8 @@ static const struct fsl_qspi_devtype_data imx7d_data = { 
	.txfifo = SZ_512,

	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,

	.ahb_buf_size = SZ_1K,

	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,

	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |

		  QUADSPI_QUIRK_USE_TDH_SETTING,

	.little_endian = true,

};
@@ -227,7 +239,8 @@ static const struct fsl_qspi_devtype_data imx6ul_data = { 
	.txfifo = SZ_512,

	.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,

	.ahb_buf_size = SZ_1K,

	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,

	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |

		  QUADSPI_QUIRK_USE_TDH_SETTING,

	.little_endian = true,

};
@@ -287,6 +300,11 @@ static inline int needs_amba_base_offset(struct fsl_qspi *q) 
	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);

}



static inline int needs_tdh_setting(struct fsl_qspi *q)

{

	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;

}



/*

 * An IC bug makes it necessary to rearrange the 32-bit data.

 * Later chips, such as IMX6SLX, have fixed this bug.
@@ -727,6 +745,16 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) 
	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,

		    base + QUADSPI_MCR);



	/*

	 * Previous boot stages (BootROM, bootloader) might have used DDR

	 * mode and did not clear the TDH bits. As we currently use SDR mode

	 * only, clear the TDH bits if necessary.

	 */

	if (needs_tdh_setting(q))

		qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &

			    ~QUADSPI_FLSHCR_TDH_MASK,

			    base + QUADSPI_FLSHCR);



	reg = qspi_readl(q, base + QUADSPI_SMPR);

	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK

			| QUADSPI_SMPR_FSPHS_MASK

drivers/spi/spi-gpio.c

+3 −1
Original line number Diff line number Diff line
@@ -368,8 +368,10 @@ static int spi_gpio_probe(struct platform_device *pdev) 
		return -ENOMEM;



	status = devm_add_action_or_reset(&pdev->dev, spi_gpio_put, master);

	if (status)

	if (status) {

		spi_master_put(master);

		return status;

	}



	if (pdev->dev.of_node)

		status = spi_gpio_probe_dt(pdev, master);

drivers/spi/spi-mxic.c

+3 −3
Original line number Diff line number Diff line
@@ -145,8 +145,8 @@ 
#define LWR_SUSP_CTRL_EN	BIT(31)



#define DMAS_CTRL		0x9c

#define DMAS_CTRL_DIR_READ	BIT(31)

#define DMAS_CTRL_EN		BIT(30)

#define DMAS_CTRL_EN		BIT(31)

#define DMAS_CTRL_DIR_READ	BIT(30)



#define DATA_STROB		0xa0

#define DATA_STROB_EDO_EN	BIT(2)
@@ -275,7 +275,7 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) 
	writel(0, mxic->regs + HC_EN);

	writel(0, mxic->regs + LRD_CFG);

	writel(0, mxic->regs + LRD_CTRL);

	writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NAND) |

	writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |

	       HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),

	       mxic->regs + HC_CFG);

}

drivers/spi/spi-orion.c

+0 −3
Original line number Diff line number Diff line
@@ -772,9 +772,6 @@ static int orion_spi_probe(struct platform_device *pdev) 
	if (status < 0)

		goto out_rel_pm;



	pm_runtime_mark_last_busy(&pdev->dev);

	pm_runtime_put_autosuspend(&pdev->dev);



	master->dev.of_node = pdev->dev.of_node;

	status = spi_register_master(master);

	if (status < 0)