Commit 2b822f47 authored by Rahul Tanwar's avatar Rahul Tanwar Committed by Thomas Gleixner
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dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema 



The DT bindings for X86 local APIC (lapic) and I/O APIC (ioapic) are
outdated. Rework them:

   - Convert the bindings for lapic and ioapic from text to YAML schema.
   - Separate lapic & ioapic schemas.
   - Add missing but required standard properties
   - Add missing descriptions

Suggested-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarRahul Tanwar <rtanwar@maxlinear.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221124084143.21841-2-rtanwar@maxlinear.com
parent 9b09927c

Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt

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Interrupt chips

---------------



* Intel I/O Advanced Programmable Interrupt Controller (IO APIC)



  Required properties:

  --------------------

     compatible = "intel,ce4100-ioapic";

     #interrupt-cells = <2>;



  Device's interrupt property:



     interrupts = <P S>;



  The first number (P) represents the interrupt pin which is wired to the

  IO APIC. The second number (S) represents the sense of interrupt which

  should be configured and can be one of:

    0 - Edge Rising

    1 - Level Low

    2 - Level High

    3 - Edge Falling



* Local APIC

  Required property:



     compatible = "intel,ce4100-lapic";

Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)



maintainers:

  - Rahul Tanwar <rtanwar@maxlinear.com>



description: |

  Intel's Advanced Programmable Interrupt Controller (APIC) is a

  family of interrupt controllers. The APIC is a split

  architecture design, with a local component (LAPIC) integrated

  into the processor itself and an external I/O APIC. Local APIC

  (lapic) receives interrupts from the processor's interrupt pins,

  from internal sources and from an external I/O APIC (ioapic).

  And it sends these to the processor core for handling.

  See [1] Chapter 8 for more details.



  Many of the Intel's generic devices like hpet, ioapic, lapic have

  the ce4100 name in their compatible property names because they

  first appeared in CE4100 SoC.



  This schema defines bindings for I/O APIC interrupt controller.



  [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf



properties:

  compatible:

    const: intel,ce4100-ioapic



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'



additionalProperties: false



examples:

  - |

    ioapic1: interrupt-controller@fec00000 {

        compatible = "intel,ce4100-ioapic";

        reg = <0xfec00000 0x1000>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };

Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)



maintainers:

  - Rahul Tanwar <rtanwar@maxlinear.com>



description: |

  Intel's Advanced Programmable Interrupt Controller (APIC) is a

  family of interrupt controllers. The APIC is a split

  architecture design, with a local component (LAPIC) integrated

  into the processor itself and an external I/O APIC. Local APIC

  (lapic) receives interrupts from the processor's interrupt pins,

  from internal sources and from an external I/O APIC (ioapic).

  And it sends these to the processor core for handling.

  See [1] Chapter 8 for more details.



  Many of the Intel's generic devices like hpet, ioapic, lapic have

  the ce4100 name in their compatible property names because they

  first appeared in CE4100 SoC.



  This schema defines bindings for local APIC interrupt controller.



  [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf



properties:

  compatible:

    const: intel,ce4100-lapic



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2



required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'



additionalProperties: false



examples:

  - |

    lapic0: interrupt-controller@fee00000 {

        compatible = "intel,ce4100-lapic";

        reg = <0xfee00000 0x1000>;

        interrupt-controller;

        #interrupt-cells = <2>;

    };