Commit 2d5a3c80 authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

arm: dra7: add DESHDCP clock 



Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
parent c65b99f0

arch/arm/boot/dts/dra7.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -131,6 +131,11 @@ pbias_mmc_reg: pbias_mmc_omap5 { 
							regulator-max-microvolt = <3000000>;

						};

					};



					scm_conf_clocks: clocks {

						#address-cells = <1>;

						#size-cells = <0>;

					};

				};



				dra7_pmx_core: pinmux@1400 {

arch/arm/boot/dts/dra7xx-clocks.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -2136,3 +2136,13 @@ coreaon_clkdm: coreaon_clkdm { 
		clocks = <&dpll_usb_ck>;

	};

};



&scm_conf_clocks {

	dss_deshdcp_clk: dss_deshdcp_clk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&l3_iclk_div>;

		ti,bit-shift = <0>;

		reg = <0x558>;

	};

};

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+1 −0
Original line number Diff line number Diff line
@@ -438,6 +438,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { 
	{ .role = "video2_clk", .clk = "dss_video2_clk" },

	{ .role = "video1_clk", .clk = "dss_video1_clk" },

	{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },

	{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },

};



static struct omap_hwmod dra7xx_dss_hwmod = {

drivers/clk/ti/clk-7xx.c

+1 −0
Original line number Diff line number Diff line
@@ -305,6 +305,7 @@ static struct ti_dt_clk dra7xx_clks[] = { 
	DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),

	DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),

	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),

	DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),

	{ .node_name = NULL },

};