Commit 2d93887c authored by Johan Hovold's avatar Johan Hovold Committed by Vinod Koul
Browse files

phy: qcom-qmp-pcie: drop bogus register update 



Since commit 0d58280c ("phy: Update PHY power control sequence") the
PHY is powered on before configuring the registers and only the MSM8996
PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS
initialisation table, may possibly require a second update afterwards.

To make things worse, the POWER_DOWN_CONTROL register lies at a
different offset on more recent SoCs so that the second update, which
still used a hard-coded offset, would write to an unrelated register
(e.g. a revision-id register on SC8280XP).

As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop
the bogus register update.

Fixes: e4d8b05a ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #RB3
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221017065013.19647-12-johan+linaro@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5b76f5ec

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+0 −6
Original line number Diff line number Diff line
@@ -2061,12 +2061,6 @@ static int qmp_pcie_power_on(struct phy *phy) 
	qmp_pcie_pcs_init(qphy, &cfg->tables);

	qmp_pcie_pcs_init(qphy, mode_tables);



	/*

	 * Pull out PHY from POWER DOWN state.

	 * This is active low enable signal to power-down PHY.

	 */

	qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);



	if (cfg->has_pwrdn_delay)

		usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);