Commit 2db34041 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.5-next-dts64' of... 

Merge tag 'v5.5-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- add dynamic power coefficient to the cpu clusters
- add jpeg decoder node

mt8183:
- add node for the Global Command Engine (gce)
- add reset cells to the infracfg node

* tag 'v5.5-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8183: add reset-cells in infracfg
  arm64: dts: mt8173: add Mediatek JPEG Codec
  arm64: dts: add gce node for mt8183
  arm64: dts: mt8173: Add dynamic power node.

Link: https://lore.kernel.org/r/46c1a244-3f74-8069-6600-8ced02775677@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7d6292ab a845ad16

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ cpu0: cpu@0 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <263>;

			clocks = <&infracfg CLK_INFRA_CA53SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";
@@ -170,6 +171,7 @@ cpu1: cpu@1 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <263>;

			clocks = <&infracfg CLK_INFRA_CA53SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";
@@ -183,6 +185,7 @@ cpu2: cpu@100 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <530>;

			clocks = <&infracfg CLK_INFRA_CA72SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";
@@ -196,6 +199,7 @@ cpu3: cpu@101 { 
			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <530>;

			clocks = <&infracfg CLK_INFRA_CA72SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";
@@ -1401,6 +1405,20 @@ vcodec_enc: vcodec@18002000 { 
						 <&topckgen CLK_TOP_UNIVPLL1_D2>;

		};



		jpegdec: jpegdec@18004000 {

			compatible = "mediatek,mt8173-jpgdec";

			reg = <0 0x18004000 0 0x1000>;

			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&vencsys CLK_VENC_CKE0>,

				 <&vencsys CLK_VENC_CKE3>;

			clock-names = "jpgdec-smi",

				      "jpgdec";

			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;

			mediatek,larb = <&larb3>;

			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,

				 <&iommu M4U_PORT_JPGDEC_BSDMA>;

		};



		vencltsys: clock-controller@19000000 {

			compatible = "mediatek,mt8173-vencltsys", "syscon";

			reg = <0 0x19000000 0 0x1000>;

arch/arm64/boot/dts/mediatek/mt8183.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/clock/mt8183-clk.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/reset-controller/mt8183-resets.h>

#include "mt8183-pinfunc.h"



/ {
@@ -227,6 +228,7 @@ infracfg: syscon@10001000 { 
			compatible = "mediatek,mt8183-infracfg", "syscon";

			reg = <0 0x10001000 0 0x1000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

		};



		pio: pinctrl@10005000 {
@@ -278,6 +280,15 @@ systimer: timer@10017000 { 
			clock-names = "clk13m";

		};



		gce: mailbox@10238000 {

			compatible = "mediatek,mt8183-gce";

			reg = <0 0x10238000 0 0x4000>;

			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;

			#mbox-cells = <3>;

			clocks = <&infracfg CLK_INFRA_GCE>;

			clock-names = "gce";

		};



		auxadc: auxadc@11001000 {

			compatible = "mediatek,mt8183-auxadc",

				     "mediatek,mt8173-auxadc";