Commit 2db7289f authored by Daniel Machon's avatar Daniel Machon Committed by Vinod Koul
Browse files

phy: sparx5-serdes: remove power up of all CMUs



CMUs should not be powered up by default anymore, so remove responsible
code.

Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 96bb1664
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+0 −25
Original line number Diff line number Diff line
@@ -1062,24 +1062,6 @@ static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)
	return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);
}

static int sparx5_serdes_cmu_enable(struct sparx5_serdes_private *priv)
{
	int idx, err = 0;

	if (!priv->cmu_enabled) {
		for (idx = 0; idx < SPX5_CMU_MAX; idx++) {
			err  = sparx5_cmu_cfg(priv, idx);
			if (err) {
				dev_err(priv->dev, "CMU %u, error: %d\n", idx, err);
				goto leave;
			}
		}
		priv->cmu_enabled = true;
	}
leave:
	return err;
}

/* Map of 6G/10G serdes mode and index to CMU index. */
static const int
sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_6G10G_CNT] = {
@@ -2236,10 +2218,6 @@ static int sparx5_serdes_config(struct sparx5_serdes_macro *macro)
	int serdesmode;
	int err;

	err = sparx5_serdes_cmu_enable(macro->priv);
	if (err)
		return err;

	serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed);
	if (serdesmode < 0) {
		dev_err(dev, "SerDes %u, interface not supported: %s\n",
@@ -2331,9 +2309,6 @@ static int sparx5_serdes_reset(struct phy *phy)
	struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
	int err;

	err = sparx5_serdes_cmu_enable(macro->priv);
	if (err)
		return err;
	if (macro->serdestype == SPX5_SDT_25G)
		err = sparx5_sd25g28_config(macro, true);
	else
+0 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ struct sparx5_serdes_private {
	struct device *dev;
	void __iomem *regs[NUM_TARGETS];
	struct phy *phys[SPX5_SERDES_MAX];
	bool cmu_enabled;
	unsigned long coreclock;
};