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Commit 2dbaa6a6 authored by Marek Vasut's avatar Marek Vasut Committed by Dinh Nguyen
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ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA 



Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 325ec920
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