Commit 2ee150cd authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: remove now superflous *_hdp operation 



All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarChunming Zhou <david1.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1b9d17db

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −1
Original line number Diff line number Diff line
@@ -1797,7 +1797,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))

#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))

#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))

#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))

#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))

#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))

#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+1 −6
Original line number Diff line number Diff line
@@ -225,12 +225,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
#ifdef CONFIG_X86_64

	if (!(adev->flags & AMD_IS_APU))

#endif

	{

		if (ring->funcs->emit_hdp_invalidate)

			amdgpu_ring_emit_hdp_invalidate(ring);

		else

		amdgpu_asic_invalidate_hdp(adev, ring);

	}



	r = amdgpu_fence_emit(ring, f);

	if (r) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+0 −1
Original line number Diff line number Diff line
@@ -128,7 +128,6 @@ struct amdgpu_ring_funcs { 
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,

			      unsigned pasid, uint64_t pd_addr);

	void (*emit_hdp_flush)(struct amdgpu_ring *ring);

	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);

	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,

				uint32_t gds_base, uint32_t gds_size,

				uint32_t gws_base, uint32_t gws_size,

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+1 −9
Original line number Diff line number Diff line
@@ -261,13 +261,6 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */

}



static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	amdgpu_ring_write(ring, mmHDP_DEBUG0);

	amdgpu_ring_write(ring, 1);

}



/**

 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring

 *
@@ -1277,7 +1270,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 
	.set_wptr = cik_sdma_ring_set_wptr,

	.emit_frame_size =

		6 + /* cik_sdma_ring_emit_hdp_flush */

		3 + /* cik_sdma_ring_emit_hdp_invalidate */

		3 + /* hdp invalidate */

		6 + /* cik_sdma_ring_emit_pipeline_sync */

		CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */

		9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
@@ -1287,7 +1280,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 
	.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,

	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,

	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,

	.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,

	.test_ring = cik_sdma_ring_test_ring,

	.test_ib = cik_sdma_ring_test_ib,

	.insert_nop = cik_sdma_ring_insert_nop,

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+2 −37
Original line number Diff line number Diff line
@@ -1809,17 +1809,6 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 
	return r;

}



static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)

{

	/* flush hdp cache */

	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

				 WRITE_DATA_DST_SEL(0)));

	amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, 0x1);

}



static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
@@ -1827,24 +1816,6 @@ static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 
		EVENT_INDEX(0));

}



/**

 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp

 *

 * @adev: amdgpu_device pointer

 * @ridx: amdgpu ring index

 *

 * Emits an hdp invalidate on the cp.

 */

static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

				 WRITE_DATA_DST_SEL(0)));

	amdgpu_ring_write(ring, mmHDP_DEBUG0);

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, 0x1);

}



static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,

				     u64 seq, unsigned flags)

{
@@ -3507,8 +3478,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 
	.get_wptr = gfx_v6_0_ring_get_wptr,

	.set_wptr = gfx_v6_0_ring_set_wptr_gfx,

	.emit_frame_size =

		5 + /* gfx_v6_0_ring_emit_hdp_flush */

		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */

		5 + 5 + /* hdp flush / invalidate */

		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */

		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */

		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
@@ -3518,8 +3488,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 
	.emit_fence = gfx_v6_0_ring_emit_fence,

	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,

	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,

	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,

	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,

	.test_ring = gfx_v6_0_ring_test_ring,

	.test_ib = gfx_v6_0_ring_test_ib,

	.insert_nop = amdgpu_ring_insert_nop,
@@ -3535,8 +3503,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 
	.get_wptr = gfx_v6_0_ring_get_wptr,

	.set_wptr = gfx_v6_0_ring_set_wptr_compute,

	.emit_frame_size =

		5 + /* gfx_v6_0_ring_emit_hdp_flush */

		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */

		5 + 5 + /* hdp flush / invalidate */

		7 + /* gfx_v6_0_ring_emit_pipeline_sync */

		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */

		14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
@@ -3545,8 +3512,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 
	.emit_fence = gfx_v6_0_ring_emit_fence,

	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,

	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,

	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,

	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,

	.test_ring = gfx_v6_0_ring_test_ring,

	.test_ib = gfx_v6_0_ring_test_ib,

	.insert_nop = amdgpu_ring_insert_nop,