Commit 2fd36aa0 authored by Andy Shevchenko's avatar Andy Shevchenko
Browse files

pwm: lpss: Allow other drivers to enable PWM LPSS 



The PWM LPSS device can be embedded in another device.
In order to enable it, allow that drivers to probe
a corresponding device.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarThierry Reding <thierry.reding@gmail.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
parent 878cf979

drivers/pwm/pwm-lpss.h

+1 −21
Original line number Original line Diff line number Diff line
@@ -13,7 +13,7 @@ 
#include <linux/pwm.h>

#include <linux/pwm.h>

#include <linux/types.h>

#include <linux/types.h>





struct device;

#include <linux/platform_data/x86/pwm-lpss.h>





#define LPSS_MAX_PWMS			4

#define LPSS_MAX_PWMS			4
@@ -23,29 +23,9 @@ struct pwm_lpss_chip { 
	const struct pwm_lpss_boardinfo *info;

	const struct pwm_lpss_boardinfo *info;

};

};





struct pwm_lpss_boardinfo {

	unsigned long clk_rate;

	unsigned int npwm;

	unsigned long base_unit_bits;

	/*

	 * Some versions of the IP may stuck in the state machine if enable

	 * bit is not set, and hence update bit will show busy status till

	 * the reset. For the rest it may be otherwise.

	 */

	bool bypass;

	/*

	 * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device

	 * messes with the PWM0 controllers state,

	 */

	bool other_devices_aml_touches_pwm_regs;

};



extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;

extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;





struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,

				     const struct pwm_lpss_boardinfo *info);



#endif	/* __PWM_LPSS_H */
 
#endif	/* __PWM_LPSS_H */

include/linux/platform_data/x86/pwm-lpss.h

0 → 100644
+33 −0
Original line number Original line Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Intel Low Power Subsystem PWM controller driver */



#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H

#define __PLATFORM_DATA_X86_PWM_LPSS_H



#include <linux/types.h>



struct device;



struct pwm_lpss_chip;



struct pwm_lpss_boardinfo {

	unsigned long clk_rate;

	unsigned int npwm;

	unsigned long base_unit_bits;

	/*

	 * Some versions of the IP may stuck in the state machine if enable

	 * bit is not set, and hence update bit will show busy status till

	 * the reset. For the rest it may be otherwise.

	 */

	bool bypass;

	/*

	 * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device

	 * messes with the PWM0 controllers state,

	 */

	bool other_devices_aml_touches_pwm_regs;

};



struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,

				     const struct pwm_lpss_boardinfo *info);



#endif	/* __PLATFORM_DATA_X86_PWM_LPSS_H */