Commit 3011e0c8 authored by Radhey Shyam Pandey's avatar Radhey Shyam Pandey Committed by Michal Simek
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arm64: zynqmp: Add L2 cache nodes 



Describe SoC L2 cache hierarchy.

Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com
parent 06c2afb8

arch/arm64/boot/dts/xilinx/zynqmp.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ cpu0: cpu@0 { 
			operating-points-v2 = <&cpu_opp_table>;

			reg = <0x0>;

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2>;

		};



		cpu1: cpu@1 {
@@ -42,6 +43,7 @@ cpu1: cpu@1 { 
			reg = <0x1>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2>;

		};



		cpu2: cpu@2 {
@@ -51,6 +53,7 @@ cpu2: cpu@2 { 
			reg = <0x2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2>;

		};



		cpu3: cpu@3 {
@@ -60,6 +63,13 @@ cpu3: cpu@3 { 
			reg = <0x3>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP_0>;

			next-level-cache = <&L2>;

		};



		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};



		idle-states {