Commit 305f0980 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: merge two duplicated clock_source_create 



[why]
dcn31x could use dcn31 sepcific which contains deep_color_ratio for dmub

Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: default avatarHansen Dsouza <hansen.dsouza@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5fed53c7

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+72 −55
Original line number Diff line number Diff line
@@ -978,9 +978,25 @@ static bool dcn31_program_pix_clk( 
		struct pll_settings *pll_settings)

{

	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

	unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

	unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

	const struct pixel_rate_range_table_entry *e =

			look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);

	struct bp_pixel_clock_parameters bp_pc_params = {0};

	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;



	// For these signal types Driver to program DP_DTO without calling VBIOS Command table

	if (dc_is_dp_signal(pix_clk_params->signal_type)) {

		if (e) {

			/* Set DTO values: phase = target clock, modulo = reference clock*/

			REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);

			REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);

		} else {

			/* Set DTO values: phase = target clock, modulo = reference clock*/

			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);

			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);

		}

		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

	} else {

		if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {

			unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

			unsigned dp_dto_ref_100hz = 7000000;
@@ -1042,6 +1058,7 @@ static bool dcn31_program_pix_clk( 
						pix_clk_params->signal_type,

						pix_clk_params->color_depth,

						pix_clk_params->flags.SUPPORT_YCBCR420);

	}



	return true;

}

drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c

+5 −28
Original line number Diff line number Diff line
@@ -1963,29 +1963,6 @@ static struct resource_funcs dcn315_res_pool_funcs = { 
	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

};



static struct clock_source *dcn30_clock_source_create(

		struct dc_context *ctx,

		struct dc_bios *bios,

		enum clock_source_id id,

		const struct dce110_clk_src_regs *regs,

		bool dp_clk_src)

{

	struct dce110_clk_src *clk_src =

		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);



	if (!clk_src)

		return NULL;



	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,

			regs, &cs_shift, &cs_mask)) {

		clk_src->base.dp_clk_src = dp_clk_src;

		return &clk_src->base;

	}



	BREAK_TO_DEBUGGER();

	return NULL;

}



static bool dcn315_resource_construct(

	uint8_t num_virtual_links,

	struct dc *dc,
@@ -2091,23 +2068,23 @@ static bool dcn315_resource_construct( 


	/* Clock Sources for Pixel Clock*/

	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL0,

				&clk_src_regs[0], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL1,

				&clk_src_regs[1], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL2,

				&clk_src_regs[2], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL3,

				&clk_src_regs[3], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL4,

				&clk_src_regs[4], false);

drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c

+5 −28
Original line number Diff line number Diff line
@@ -1964,29 +1964,6 @@ static struct resource_funcs dcn316_res_pool_funcs = { 
	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

};



static struct clock_source *dcn30_clock_source_create(

		struct dc_context *ctx,

		struct dc_bios *bios,

		enum clock_source_id id,

		const struct dce110_clk_src_regs *regs,

		bool dp_clk_src)

{

	struct dce110_clk_src *clk_src =

		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);



	if (!clk_src)

		return NULL;



	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,

			regs, &cs_shift, &cs_mask)) {

		clk_src->base.dp_clk_src = dp_clk_src;

		return &clk_src->base;

	}



	BREAK_TO_DEBUGGER();

	return NULL;

}



static bool dcn316_resource_construct(

	uint8_t num_virtual_links,

	struct dc *dc,
@@ -2092,23 +2069,23 @@ static bool dcn316_resource_construct( 


	/* Clock Sources for Pixel Clock*/

	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL0,

				&clk_src_regs[0], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL1,

				&clk_src_regs[1], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL2,

				&clk_src_regs[2], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL3,

				&clk_src_regs[3], false);

	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =

			dcn30_clock_source_create(ctx, ctx->dc_bios,

			dcn31_clock_source_create(ctx, ctx->dc_bios,

				CLOCK_SOURCE_COMBO_PHY_PLL4,

				&clk_src_regs[4], false);