Unverified Commit 33423a8b authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'juno-updates-6.2' of... 

Merge tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt

Armv8 Juno/FVP updates for v6.2

Just few addtions including updates to cache information on various
platforms to align well with the bindings, addition of cache information
on FVP Rev C model, addition of SPE to Foundation model and updates to
LED node names.

* tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  ARM: dts: vexpress: align LED node names with dtschema
  arm64: dts: fvp: Add information about L1 and L2 caches
  arm64: dts: fvp: Add SPE to Foundation FVP
  arm64: dts: Update cache properties for Arm Ltd platforms
  arm64: dts: juno: Add thermal critical trip points

Link: https://lore.kernel.org/r/20221129115111.2464233-1-sudeep.holla@arm.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7b16ab92 e1503153

arch/arm/boot/dts/vexpress-v2m.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -383,49 +383,49 @@ v2m_refclk32khz: refclk32khz { 
			leds {

				compatible = "gpio-leds";



				user1 {

				led-user1 {

					label = "v2m:green:user1";

					gpios = <&v2m_led_gpios 0 0>;

					linux,default-trigger = "heartbeat";

				};



				user2 {

				led-user2 {

					label = "v2m:green:user2";

					gpios = <&v2m_led_gpios 1 0>;

					linux,default-trigger = "mmc0";

				};



				user3 {

				led-user3 {

					label = "v2m:green:user3";

					gpios = <&v2m_led_gpios 2 0>;

					linux,default-trigger = "cpu0";

				};



				user4 {

				led-user4 {

					label = "v2m:green:user4";

					gpios = <&v2m_led_gpios 3 0>;

					linux,default-trigger = "cpu1";

				};



				user5 {

				led-user5 {

					label = "v2m:green:user5";

					gpios = <&v2m_led_gpios 4 0>;

					linux,default-trigger = "cpu2";

				};



				user6 {

				led-user6 {

					label = "v2m:green:user6";

					gpios = <&v2m_led_gpios 5 0>;

					linux,default-trigger = "cpu3";

				};



				user7 {

				led-user7 {

					label = "v2m:green:user7";

					gpios = <&v2m_led_gpios 6 0>;

					linux,default-trigger = "cpu4";

				};



				user8 {

				led-user8 {

					label = "v2m:green:user8";

					gpios = <&v2m_led_gpios 7 0>;

					linux,default-trigger = "cpu5";

arch/arm64/boot/dts/arm/corstone1000.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 { 


	L2_0: l2-cache0 {

		compatible = "cache";

		cache-unified;

		cache-level = <2>;

		cache-size = <0x80000>;

		cache-line-size = <64>;

arch/arm64/boot/dts/arm/foundation-v8.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ cpu3: cpu@3 { 


		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};

	};
@@ -84,6 +85,11 @@ pmu { 
			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

	};



	spe-pmu {

		compatible = "arm,statistical-profiling-extension-v1";

		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;

	};



	watchdog@2a440000 {

		compatible = "arm,sbsa-gwdt";

		reg = <0x0 0x2a440000 0 0x1000>,

arch/arm64/boot/dts/arm/fvp-base-revc.dts

+73 −0
Original line number Diff line number Diff line
@@ -47,48 +47,121 @@ cpu0: cpu@0 { 
			compatible = "arm,armv8";

			reg = <0x0 0x000>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C0_L2>;

		};

		cpu4: cpu@10000 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10000>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu5: cpu@10100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10100>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu6: cpu@10200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10200>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		cpu7: cpu@10300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x10300>;

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&C1_L2>;

		};

		C0_L2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};



		C1_L2: l2-cache1 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/arm/juno-base.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -751,12 +751,26 @@ pmic { 
			polling-delay = <1000>;

			polling-delay-passive = <100>;

			thermal-sensors = <&scpi_sensors0 0>;

			trips {

				pmic_crit0: trip0 {

					temperature = <90000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};

		};



		soc {

			polling-delay = <1000>;

			polling-delay-passive = <100>;

			thermal-sensors = <&scpi_sensors0 3>;

			trips {

				soc_crit0: trip0 {

					temperature = <80000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};

		};



		big_cluster_thermal_zone: big-cluster {