Loading drivers/ssb/driver_chipcommon.c +1 −1 Original line number Diff line number Diff line Loading @@ -354,7 +354,7 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) if (cc->dev->id.revision >= 11) cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); ssb_dbg("chipcommon status is 0x%x\n", cc->status); if (cc->dev->id.revision >= 20) { chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); Loading drivers/ssb/driver_chipcommon_pmu.c +18 −23 Original line number Diff line number Diff line Loading @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, return; } ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", (crystalfreq / 1000), (crystalfreq % 1000)); ssb_info("Programming PLL to %u.%03u MHz\n", crystalfreq / 1000, crystalfreq % 1000); /* First turn the PLL off. */ switch (bus->chip_id) { Loading @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, } tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ssb_emerg("Failed to turn the PLL off!\n"); /* Set PDIV in PLL control 0. */ pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); Loading Loading @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, return; } ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", (crystalfreq / 1000), (crystalfreq % 1000)); ssb_info("Programming PLL to %u.%03u MHz\n", crystalfreq / 1000, crystalfreq % 1000); /* First turn the PLL off. */ switch (bus->chip_id) { Loading @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, } tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ssb_emerg("Failed to turn the PLL off!\n"); /* Set p1div and p2div. */ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); Loading Loading @@ -349,8 +349,7 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc) case 43222: break; default: ssb_printk(KERN_ERR PFX "ERROR: PLL init unknown for device %04X\n", ssb_err("ERROR: PLL init unknown for device %04X\n", bus->chip_id); } } Loading Loading @@ -472,8 +471,7 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc) max_msk = 0xFFFFF; break; default: ssb_printk(KERN_ERR PFX "ERROR: PMU resource config unknown for device %04X\n", ssb_err("ERROR: PMU resource config unknown for device %04X\n", bus->chip_id); } Loading Loading @@ -526,7 +524,7 @@ void ssb_pmu_init(struct ssb_chipcommon *cc) pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); if (cc->pmu.rev == 1) Loading Loading @@ -638,8 +636,7 @@ u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc) case 0x5354: ssb_pmu_get_alp_clock_clk0(cc); default: ssb_printk(KERN_ERR PFX "ERROR: PMU alp clock unknown for device %04X\n", ssb_err("ERROR: PMU alp clock unknown for device %04X\n", bus->chip_id); return 0; } Loading @@ -654,8 +651,7 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) /* 5354 chip uses a non programmable PLL of frequency 240MHz */ return 240000000; default: ssb_printk(KERN_ERR PFX "ERROR: PMU cpu clock unknown for device %04X\n", ssb_err("ERROR: PMU cpu clock unknown for device %04X\n", bus->chip_id); return 0; } Loading @@ -669,8 +665,7 @@ u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc) case 0x5354: return 120000000; default: ssb_printk(KERN_ERR PFX "ERROR: PMU controlclock unknown for device %04X\n", ssb_err("ERROR: PMU controlclock unknown for device %04X\n", bus->chip_id); return 0; } Loading drivers/ssb/driver_mipscore.c +13 −12 Original line number Diff line number Diff line Loading @@ -167,21 +167,22 @@ static void set_irq(struct ssb_device *dev, unsigned int irq) irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]); ssb_write32(mdev, SSB_IPSFLAG, irqflag); } ssb_dprintk(KERN_INFO PFX "set_irq: core 0x%04x, irq %d => %d\n", ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n", dev->id.coreid, oldirq+2, irq+2); } static void print_irq(struct ssb_device *dev, unsigned int irq) { int i; static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; ssb_dprintk(KERN_INFO PFX "core 0x%04x, irq :", dev->id.coreid); for (i = 0; i <= 6; i++) { ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" "); } ssb_dprintk("\n"); ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n", dev->id.coreid, irq_name[0], irq == 0 ? "*" : " ", irq_name[1], irq == 1 ? "*" : " ", irq_name[2], irq == 2 ? "*" : " ", irq_name[3], irq == 3 ? "*" : " ", irq_name[4], irq == 4 ? "*" : " ", irq_name[5], irq == 5 ? "*" : " ", irq_name[6], irq == 6 ? "*" : " "); } static void dump_irq(struct ssb_bus *bus) Loading Loading @@ -286,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore) if (!mcore->dev) return; /* We don't have a MIPS core */ ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); ssb_dbg("Initializing MIPS core...\n"); bus = mcore->dev->bus; hz = ssb_clockspeed(bus); Loading Loading @@ -334,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore) break; } } ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); ssb_dbg("after irq reconfiguration\n"); dump_irq(bus); ssb_mips_serial_init(mcore); Loading drivers/ssb/driver_pcicore.c +7 −8 Original line number Diff line number Diff line Loading @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci_dev *d) return -ENODEV; } ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", pci_name(d)); ssb_info("PCI: Fixing up device %s\n", pci_name(d)); /* Fix up interrupt lines */ d->irq = ssb_mips_irq(extpci_core->dev) + 2; Loading @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) return; ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev)); /* Enable PCI bridge bus mastering and memory space */ pci_set_master(dev); if (pcibios_enable_device(dev, ~0) < 0) { ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); ssb_err("PCI: SSB bridge enable failed\n"); return; } Loading @@ -299,7 +298,7 @@ static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) /* Make sure our latency is high enough to handle the devices behind us */ lat = 168; ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", ssb_info("PCI: Fixing latency timer of device %s to %u\n", pci_name(dev), lat); pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); } Loading @@ -323,7 +322,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) return; extpci_core = pc; ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); ssb_dbg("PCIcore in host mode found\n"); /* Reset devices on the external PCI bus */ val = SSB_PCICORE_CTL_RST_OE; val |= SSB_PCICORE_CTL_CLK_OE; Loading @@ -338,7 +337,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) udelay(1); /* Assertion time demanded by the PCI standard */ if (pc->dev->bus->has_cardbus_slot) { ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); ssb_dbg("CardBus slot detected\n"); pc->cardbusmode = 1; /* GPIO 1 resets the bridge */ ssb_gpio_out(pc->dev->bus, 1, 1); Loading drivers/ssb/embedded.c +2 −3 Original line number Diff line number Diff line Loading @@ -57,8 +57,7 @@ int ssb_watchdog_register(struct ssb_bus *bus) bus->busnumber, &wdt, sizeof(wdt)); if (IS_ERR(pdev)) { ssb_dprintk(KERN_INFO PFX "can not register watchdog device, err: %li\n", ssb_dbg("can not register watchdog device, err: %li\n", PTR_ERR(pdev)); return PTR_ERR(pdev); } Loading Loading
drivers/ssb/driver_chipcommon.c +1 −1 Original line number Diff line number Diff line Loading @@ -354,7 +354,7 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) if (cc->dev->id.revision >= 11) cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); ssb_dbg("chipcommon status is 0x%x\n", cc->status); if (cc->dev->id.revision >= 20) { chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); Loading
drivers/ssb/driver_chipcommon_pmu.c +18 −23 Original line number Diff line number Diff line Loading @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, return; } ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", (crystalfreq / 1000), (crystalfreq % 1000)); ssb_info("Programming PLL to %u.%03u MHz\n", crystalfreq / 1000, crystalfreq % 1000); /* First turn the PLL off. */ switch (bus->chip_id) { Loading @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, } tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ssb_emerg("Failed to turn the PLL off!\n"); /* Set PDIV in PLL control 0. */ pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); Loading Loading @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, return; } ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", (crystalfreq / 1000), (crystalfreq % 1000)); ssb_info("Programming PLL to %u.%03u MHz\n", crystalfreq / 1000, crystalfreq % 1000); /* First turn the PLL off. */ switch (bus->chip_id) { Loading @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, } tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); ssb_emerg("Failed to turn the PLL off!\n"); /* Set p1div and p2div. */ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); Loading Loading @@ -349,8 +349,7 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc) case 43222: break; default: ssb_printk(KERN_ERR PFX "ERROR: PLL init unknown for device %04X\n", ssb_err("ERROR: PLL init unknown for device %04X\n", bus->chip_id); } } Loading Loading @@ -472,8 +471,7 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc) max_msk = 0xFFFFF; break; default: ssb_printk(KERN_ERR PFX "ERROR: PMU resource config unknown for device %04X\n", ssb_err("ERROR: PMU resource config unknown for device %04X\n", bus->chip_id); } Loading Loading @@ -526,7 +524,7 @@ void ssb_pmu_init(struct ssb_chipcommon *cc) pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); if (cc->pmu.rev == 1) Loading Loading @@ -638,8 +636,7 @@ u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc) case 0x5354: ssb_pmu_get_alp_clock_clk0(cc); default: ssb_printk(KERN_ERR PFX "ERROR: PMU alp clock unknown for device %04X\n", ssb_err("ERROR: PMU alp clock unknown for device %04X\n", bus->chip_id); return 0; } Loading @@ -654,8 +651,7 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) /* 5354 chip uses a non programmable PLL of frequency 240MHz */ return 240000000; default: ssb_printk(KERN_ERR PFX "ERROR: PMU cpu clock unknown for device %04X\n", ssb_err("ERROR: PMU cpu clock unknown for device %04X\n", bus->chip_id); return 0; } Loading @@ -669,8 +665,7 @@ u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc) case 0x5354: return 120000000; default: ssb_printk(KERN_ERR PFX "ERROR: PMU controlclock unknown for device %04X\n", ssb_err("ERROR: PMU controlclock unknown for device %04X\n", bus->chip_id); return 0; } Loading
drivers/ssb/driver_mipscore.c +13 −12 Original line number Diff line number Diff line Loading @@ -167,21 +167,22 @@ static void set_irq(struct ssb_device *dev, unsigned int irq) irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]); ssb_write32(mdev, SSB_IPSFLAG, irqflag); } ssb_dprintk(KERN_INFO PFX "set_irq: core 0x%04x, irq %d => %d\n", ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n", dev->id.coreid, oldirq+2, irq+2); } static void print_irq(struct ssb_device *dev, unsigned int irq) { int i; static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; ssb_dprintk(KERN_INFO PFX "core 0x%04x, irq :", dev->id.coreid); for (i = 0; i <= 6; i++) { ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" "); } ssb_dprintk("\n"); ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n", dev->id.coreid, irq_name[0], irq == 0 ? "*" : " ", irq_name[1], irq == 1 ? "*" : " ", irq_name[2], irq == 2 ? "*" : " ", irq_name[3], irq == 3 ? "*" : " ", irq_name[4], irq == 4 ? "*" : " ", irq_name[5], irq == 5 ? "*" : " ", irq_name[6], irq == 6 ? "*" : " "); } static void dump_irq(struct ssb_bus *bus) Loading Loading @@ -286,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore) if (!mcore->dev) return; /* We don't have a MIPS core */ ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); ssb_dbg("Initializing MIPS core...\n"); bus = mcore->dev->bus; hz = ssb_clockspeed(bus); Loading Loading @@ -334,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore) break; } } ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); ssb_dbg("after irq reconfiguration\n"); dump_irq(bus); ssb_mips_serial_init(mcore); Loading
drivers/ssb/driver_pcicore.c +7 −8 Original line number Diff line number Diff line Loading @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci_dev *d) return -ENODEV; } ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", pci_name(d)); ssb_info("PCI: Fixing up device %s\n", pci_name(d)); /* Fix up interrupt lines */ d->irq = ssb_mips_irq(extpci_core->dev) + 2; Loading @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) return; ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev)); /* Enable PCI bridge bus mastering and memory space */ pci_set_master(dev); if (pcibios_enable_device(dev, ~0) < 0) { ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); ssb_err("PCI: SSB bridge enable failed\n"); return; } Loading @@ -299,7 +298,7 @@ static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) /* Make sure our latency is high enough to handle the devices behind us */ lat = 168; ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", ssb_info("PCI: Fixing latency timer of device %s to %u\n", pci_name(dev), lat); pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); } Loading @@ -323,7 +322,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) return; extpci_core = pc; ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); ssb_dbg("PCIcore in host mode found\n"); /* Reset devices on the external PCI bus */ val = SSB_PCICORE_CTL_RST_OE; val |= SSB_PCICORE_CTL_CLK_OE; Loading @@ -338,7 +337,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) udelay(1); /* Assertion time demanded by the PCI standard */ if (pc->dev->bus->has_cardbus_slot) { ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); ssb_dbg("CardBus slot detected\n"); pc->cardbusmode = 1; /* GPIO 1 resets the bridge */ ssb_gpio_out(pc->dev->bus, 1, 1); Loading
drivers/ssb/embedded.c +2 −3 Original line number Diff line number Diff line Loading @@ -57,8 +57,7 @@ int ssb_watchdog_register(struct ssb_bus *bus) bus->busnumber, &wdt, sizeof(wdt)); if (IS_ERR(pdev)) { ssb_dprintk(KERN_INFO PFX "can not register watchdog device, err: %li\n", ssb_dbg("can not register watchdog device, err: %li\n", PTR_ERR(pdev)); return PTR_ERR(pdev); } Loading