Commit 33b97cf8 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: add more parameters and functions to amdgpu_umc structure 



expose more parameters and functions of specific umc version to common
umc layer, so amdgpu_umc layer and other blocks could access them

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a55c8d7b

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

+13 −0
Original line number Diff line number Diff line
@@ -22,15 +22,28 @@ 
#define __AMDGPU_UMC_H__



struct amdgpu_umc_funcs {

	void (*ras_init)(struct amdgpu_device *adev);

	void (*query_ras_error_count)(struct amdgpu_device *adev,

					void *ras_error_status);

	void (*query_ras_error_address)(struct amdgpu_device *adev,

					void *ras_error_status);

	void (*enable_umc_index_mode)(struct amdgpu_device *adev,

					uint32_t umc_instance);

	void (*disable_umc_index_mode)(struct amdgpu_device *adev);

};



struct amdgpu_umc {

	/* max error count in one ras query call */

	uint32_t max_ras_err_cnt_per_query;

	/* number of umc channel instance with memory map register access */

	uint32_t channel_inst_num;

	/* number of umc instance with memory map register access */

	uint32_t umc_inst_num;

	/* UMC regiser per channel offset */

	uint32_t channel_offs;

	/* channel index table of interleaved memory */

	const uint32_t *channel_idx_tbl;



	const struct amdgpu_umc_funcs *funcs;

};

drivers/gpu/drm/amd/amdgpu/umc_v6_1.h

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define UMC_V6_1_CHANNEL_INSTANCE_NUM		4

/* number of umc instance with memory map register access */

#define UMC_V6_1_UMC_INSTANCE_NUM		8

/* total channel instances in one umc block */

#define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)

/* UMC regiser per channel offset */

#define UMC_V6_1_PER_CHANNEL_OFFSET		0x800