Unverified Commit 34e582b5 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
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ALSA: hda: add HDaudio Extended link definitions 



Add new definitions for the HDaudio Extended link support,
specifically new registers for SoundWire, Intel DMIC and INTEL SSP
interfaces.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarTakashi Iwai <tiwai@suse.de>
Link: https://lore.kernel.org/r/20230404104127.5629-3-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent c7a92574

include/sound/hda_register.h

+38 −2
Original line number Diff line number Diff line
@@ -258,14 +258,27 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 
#define AZX_ML_BASE			0x40

#define AZX_ML_INTERVAL			0x40



/* HDaudio registers valid for HDaudio and HDaudio extended links */

#define AZX_REG_ML_LCAP			0x00

#define AZX_REG_ML_LCTL			0x04



#define AZX_ML_HDA_LCAP_ALT		BIT(28)

#define AZX_ML_HDA_LCAP_ALT_HDA		0x0

#define AZX_ML_HDA_LCAP_ALT_HDA_EXT	0x1



#define AZX_ML_HDA_LCAP_INTC		BIT(27)		/* only used if ALT == 1 */

#define AZX_ML_HDA_LCAP_OFLS		BIT(26)		/* only used if ALT == 1 */

#define AZX_ML_HDA_LCAP_LSS		BIT(23)		/* only used if ALT == 1 */

#define AZX_ML_HDA_LCAP_SLCOUNT		GENMASK(22, 20)	/* only used if ALT == 1 */



#define AZX_REG_ML_LCTL			0x04

#define AZX_ML_LCTL_INTSTS		BIT(31)		/* only used if ALT == 1 */

#define AZX_ML_LCTL_CPA			BIT(23)

#define AZX_ML_LCTL_CPA_SHIFT		23

#define AZX_ML_LCTL_SPA			BIT(16)

#define AZX_ML_LCTL_SPA_SHIFT		16

#define AZX_ML_LCTL_SCF			GENMASK(3, 0)

#define AZX_ML_LCTL_INTEN		BIT(5)		/* only used if ALT == 1 */

#define AZX_ML_LCTL_OFLEN		BIT(4)		/* only used if ALT == 1 */

#define AZX_ML_LCTL_SCF			GENMASK(3, 0)	/* only used if ALT == 0 */



#define AZX_REG_ML_LOSIDV		0x08
@@ -273,12 +286,35 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 
#define AZX_ML_LOSIDV_STREAM_MASK	0xFFFE



#define AZX_REG_ML_LSDIID		0x0C

#define AZX_REG_ML_LSDIID_OFFSET(x)	(0x0C + (x) * 0x02)	/* only used if ALT == 1 */



/* HDaudio registers only valid if LCAP.ALT == 0 */

#define AZX_REG_ML_LPSOO		0x10

#define AZX_REG_ML_LPSIO		0x12

#define AZX_REG_ML_LWALFC		0x18

#define AZX_REG_ML_LOUTPAY		0x20

#define AZX_REG_ML_LINPAY		0x30



/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */

#define AZX_REG_ML_LSYNC		0x1C



#define AZX_REG_ML_LSYNC_CMDSYNC	BIT(24)

#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT	24

#define AZX_REG_ML_LSYNC_SYNCGO		BIT(23)

#define AZX_REG_ML_LSYNC_SYNCPU		BIT(20)

#define AZX_REG_ML_LSYNC_SYNCPRD	GENMASK(19, 0)



#define AZX_REG_ML_LEPTR		0x20



#define AZX_REG_ML_LEPTR_ID		GENMASK(31, 24)

#define AZX_REG_ML_LEPTR_ID_SHIFT	24

#define AZX_REG_ML_LEPTR_ID_SDW		0x00

#define AZX_REG_ML_LEPTR_ID_INTEL_SSP	0xC0

#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC  0xC1

#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL  0xC2

#define AZX_REG_ML_LEPTR_VER		GENMASK(23, 20)

#define AZX_REG_ML_LEPTR_PTR		GENMASK(19, 0)



/* registers for DMA Resume Capability Structure */

#define AZX_DRSM_CAP_ID			0x5

#define AZX_REG_DRSM_CTL		0x4