Loading drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ struct nvkm_top { u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx); u32 nvkm_top_intr(struct nvkm_device *, u32 intr, u64 *subdevs); u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx); enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault); enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); Loading drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c +16 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,22 @@ nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) return 0; } u32 nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { if (info->index == devidx && info->intr >= 0) return BIT(info->intr); } } return 0; } u32 nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) { Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ struct nvkm_top { u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx); u32 nvkm_top_intr(struct nvkm_device *, u32 intr, u64 *subdevs); u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx); enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault); enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); Loading
drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c +16 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,22 @@ nvkm_top_reset(struct nvkm_device *device, enum nvkm_devidx index) return 0; } u32 nvkm_top_intr_mask(struct nvkm_device *device, enum nvkm_devidx devidx) { struct nvkm_top *top = device->top; struct nvkm_top_device *info; if (top) { list_for_each_entry(info, &top->device, head) { if (info->index == devidx && info->intr >= 0) return BIT(info->intr); } } return 0; } u32 nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) { Loading