Commit 369b7d04 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12 



It's used internally by firmware.  Using it in the driver
could conflict with firmware.

v2: squash in fix for navi1x (Alex)

Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a0f9f854

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+4 −1
Original line number Diff line number Diff line
@@ -1134,12 +1134,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(2, 3, 0):

	case IP_VERSION(2, 3, 1):

	case IP_VERSION(2, 3, 2):

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

		break;

	case IP_VERSION(3, 3, 0):

	case IP_VERSION(3, 3, 1):

	case IP_VERSION(3, 3, 2):

	case IP_VERSION(3, 3, 3):

		adev->nbio.funcs = &nbio_v2_3_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;

		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;

		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+31 −0
Original line number Diff line number Diff line
@@ -53,6 +53,16 @@ 


#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288



#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK	0x00001000L /* Don't use.  Firmware uses this bit internally */

#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK	0x00002000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK	0x00004000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK	0x00008000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK	0x00010000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK	0x00020000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK	0x00040000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK	0x00080000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK	0x00100000L



static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -318,6 +328,27 @@ const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 
	.ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,

};



const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc = {

	.ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,

	.ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,

	.ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,

	.ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,

	.ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,

	.ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,

	.ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,

	.ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,

	.ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,

	.ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,

	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,

	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,

	.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,

	.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,

	.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,

	.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK,

	.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK,

	.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK,

};



static void nbio_v2_3_init_registers(struct amdgpu_device *adev)

{

	uint32_t def, data;

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include "soc15_common.h"



extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;

extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc;

extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;



#endif