Commit 36bbfdb8 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/adreno: Allow larger address space size 



The restriction to 4G was strictly to work around 64b math bug in some
versions of SQE firmware.  This appears to be fixed in a650+ SQE fw, so
allow a larger address space size on these devices.

Also, add a modparam override for debugging and igt.

v2: Send the right version of the patch (ie. the one that actually
    compiles)

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarChia-I Wu <olvaffe@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/487601/
Link: https://lore.kernel.org/r/20220529180428.2577832-1-robdclark@gmail.com
parent 9bec4399

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −1
Original line number Diff line number Diff line
@@ -1799,7 +1799,8 @@ a6xx_create_private_address_space(struct msm_gpu *gpu) 
		return ERR_CAST(mmu);



	return msm_gem_address_space_create(mmu,

		"gpu", 0x100000000ULL, SZ_4G);

		"gpu", 0x100000000ULL,

		adreno_private_address_space_size(gpu));

}



static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)

drivers/gpu/drm/msm/adreno/adreno_device.c

+3 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a6xx_gpu_init,

		.zapfw = "a650_zap.mdt",

		.hwcg = a650_hwcg,

		.address_space_size = SZ_16G,

	}, {

		.rev = ADRENO_REV(6, 6, 0, ANY_ID),

		.revn = 660,
@@ -329,6 +330,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a6xx_gpu_init,

		.zapfw = "a660_zap.mdt",

		.hwcg = a660_hwcg,

		.address_space_size = SZ_16G,

	}, {

		.rev = ADRENO_REV(6, 3, 5, ANY_ID),

		.fw = {
@@ -339,6 +341,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.hwcg = a660_hwcg,

		.address_space_size = SZ_16G,

	}, {

		.rev = ADRENO_REV(6, 8, 0, ANY_ID),

		.revn = 680,

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+17 −0
Original line number Diff line number Diff line
@@ -21,6 +21,10 @@ 
#include "msm_gem.h"

#include "msm_mmu.h"



static u64 address_space_size = 0;

MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");

module_param(address_space_size, ullong, 0600);



static bool zap_available = true;



static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
@@ -228,6 +232,19 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, 
	return aspace;

}



u64 adreno_private_address_space_size(struct msm_gpu *gpu)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);



	if (address_space_size)

		return address_space_size;



	if (adreno_gpu->info->address_space_size)

		return adreno_gpu->info->address_space_size;



	return SZ_4G;

}



int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,

		     uint32_t param, uint64_t *value, uint32_t *len)

{

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ struct adreno_info { 
	const char *zapfw;

	u32 inactive_period;

	const struct adreno_reglist *hwcg;

	u64 address_space_size;

};



const struct adreno_info *adreno_info(struct adreno_rev rev);
@@ -290,6 +291,7 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) 
	return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);

}



u64 adreno_private_address_space_size(struct msm_gpu *gpu);

int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,

		     uint32_t param, uint64_t *value, uint32_t *len);

int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,