Commit 37362c77 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields 



Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 268 bytes.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
parent 34856c50

drivers/pinctrl/renesas/pfc-r8a77970.c

+29 −93
Original line number Diff line number Diff line
@@ -231,7 +231,6 @@ 
#define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP8_31_28	F_(0, 0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0)



#define PINMUX_GPSR	\

\
@@ -290,8 +289,7 @@ FM(IP8_11_8) IP8_11_8 \ 
FM(IP8_15_12)	IP8_15_12 \

FM(IP8_19_16)	IP8_19_16 \

FM(IP8_23_20)	IP8_23_20 \

FM(IP8_27_24)	IP8_27_24 \

FM(IP8_31_28)	IP8_31_28

FM(IP8_27_24)	IP8_27_24



/* MOD_SEL0 */		/* 0 */			/* 1 */

#define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
@@ -2085,17 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = { 
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

#define F_(x, y)	FN_##y

#define FM(x)		FN_##x

	{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,

			     GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP0_31_22 RESERVED */

		GP_0_21_FN,	GPSR0_21,

		GP_0_20_FN,	GPSR0_20,

		GP_0_19_FN,	GPSR0_19,
@@ -2153,22 +2145,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_1_1_FN,	GPSR1_1,

		GP_1_0_FN,	GPSR1_0, ))

	},

	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,

			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP2_31_17 RESERVED */

		GP_2_16_FN,	GPSR2_16,

		GP_2_15_FN,	GPSR2_15,

		GP_2_14_FN,	GPSR2_14,
@@ -2187,22 +2168,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_2_1_FN,	GPSR2_1,

		GP_2_0_FN,	GPSR2_0, ))

	},

	{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,

			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP3_31_17 RESERVED */

		GP_3_16_FN,	GPSR3_16,

		GP_3_15_FN,	GPSR3_15,

		GP_3_14_FN,	GPSR3_14,
@@ -2221,33 +2191,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_3_1_FN,	GPSR3_1,

		GP_3_0_FN,	GPSR3_0, ))

	},

	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,

			     GROUP(-26, 1, 1, 1, 1, 1, 1),

			     GROUP(

		/* GP4_31_6 RESERVED */

		GP_4_5_FN,	GPSR4_5,

		GP_4_4_FN,	GPSR4_4,

		GP_4_3_FN,	GPSR4_3,
@@ -2255,24 +2202,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		GP_4_1_FN,	GPSR4_1,

		GP_4_0_FN,	GPSR4_0, ))

	},

	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

		0, 0,

	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,

			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,

				   1, 1, 1, 1),

			     GROUP(

		/* GP5_31_15 RESERVED */

		GP_5_14_FN,	GPSR5_14,

		GP_5_13_FN,	GPSR5_13,

		GP_5_12_FN,	GPSR5_12,
@@ -2374,8 +2308,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		IP7_7_4

		IP7_3_0 ))

	},

	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(

		IP8_31_28

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,

			      GROUP(-4, 4, 4, 4, 4, 4, 4, 4),

			      GROUP(

		/* IP8_31_28 RESERVED */

		IP8_27_24

		IP8_23_20

		IP8_19_16