Commit 37622bae authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_MMFR0_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates. The scripts would like to follow exactly what is in the
arm-arm, which uses lower case for some of these feature names.

Ensure symbols for the ID_MMFR0_EL1 register have an _EL1 suffix,
and use lower case in feature names where the arm-arm does the same.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-2-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent f0c4d9fc

arch/arm64/include/asm/sysreg.h

+8 −8
Original line number Diff line number Diff line
@@ -733,14 +733,14 @@ 
#define ID_ISAR6_DP_SHIFT		4

#define ID_ISAR6_JSCVT_SHIFT		0



#define ID_MMFR0_INNERSHR_SHIFT		28

#define ID_MMFR0_FCSE_SHIFT		24

#define ID_MMFR0_AUXREG_SHIFT		20

#define ID_MMFR0_TCM_SHIFT		16

#define ID_MMFR0_SHARELVL_SHIFT		12

#define ID_MMFR0_OUTERSHR_SHIFT		8

#define ID_MMFR0_PMSA_SHIFT		4

#define ID_MMFR0_VMSA_SHIFT		0

#define ID_MMFR0_EL1_InnerShr_SHIFT	28

#define ID_MMFR0_EL1_FCSE_SHIFT		24

#define ID_MMFR0_EL1_AuxReg_SHIFT	20

#define ID_MMFR0_EL1_TCM_SHIFT		16

#define ID_MMFR0_EL1_ShareLvl_SHIFT	12

#define ID_MMFR0_EL1_OuterShr_SHIFT	8

#define ID_MMFR0_EL1_PMSA_SHIFT		4

#define ID_MMFR0_EL1_VMSA_SHIFT		0



#define ID_MMFR4_EVT_SHIFT		28

#define ID_MMFR4_CCIDX_SHIFT		24

arch/arm64/kernel/cpufeature.c

+8 −8
Original line number Diff line number Diff line
@@ -402,14 +402,14 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 
};



static const struct arm64_ftr_bits ftr_id_mmfr0[] = {

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),

	ARM64_FTR_END,

};