Commit 38077cb3 authored by Fabien Parent's avatar Fabien Parent Committed by Matthias Brugger
Browse files

soc: mediatek: mt8365-mmsys: add DPI/HDMI display path 



Right now only the DSI path connections are described in the mt8365
mmsys driver. The external path will be DPI/HDMI. This commit adds
the connections for DPI/HDMI.

Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20220530201436.902505-5-fparent@baylibre.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 141311b8

drivers/soc/mediatek/mt8365-mmsys.h

+22 −0
Original line number Diff line number Diff line
@@ -10,6 +10,9 @@ 
#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60

#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64

#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68

#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL	0xfd0

#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN		0xfd8

#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00	0xfdc



#define MT8365_RDMA0_SOUT_COLOR0			0x1

#define MT8365_DITHER_MOUT_EN_DSI0			0x1
@@ -18,6 +21,10 @@ 
#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0

#define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0

#define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)

#define MT8365_RDMA1_SOUT_DPI0				0x1

#define MT8365_DPI0_SEL_IN_RDMA1			0x0

#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK		0x1

#define MT8365_DPI0_SEL_IN_RDMA1			0x0



static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {

	{
@@ -55,6 +62,21 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { 
		MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,

		MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0

	},

	{

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,

		MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK

	},

	{

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,

		MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1

	},

	{

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,

		MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0

	},

};



#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */