Commit 38298ce6 authored by Stanley.Yang's avatar Stanley.Yang Committed by Alex Deucher
Browse files

drm/amdgpu: Optimize checking ras supported



Using "is_app_apu" to identify device in the native
APU mode or carveout mode.

Signed-off-by: default avatarStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6fac3964
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+1 −1
Original line number Diff line number Diff line
@@ -1673,7 +1673,7 @@ int psp_ras_initialize(struct psp_context *psp)

	if (amdgpu_ras_is_poison_mode_supported(adev))
		ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
	if (!adev->gmc.xgmi.connected_to_cpu)
	if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
		ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
	ras_cmd->ras_in_message.init_flags.xcc_mask =
		adev->gfx.xcc_mask;
+3 −5
Original line number Diff line number Diff line
@@ -1686,7 +1686,6 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
		}
	}

	if (!adev->gmc.xgmi.connected_to_cpu)
	amdgpu_umc_poison_handler(adev, false);

	if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
@@ -2452,11 +2451,10 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
{
	adev->ras_hw_enabled = adev->ras_enabled = 0;

	if (!adev->is_atom_fw ||
	    !amdgpu_ras_asic_supported(adev))
	if (!amdgpu_ras_asic_supported(adev))
		return;

	if (!adev->gmc.xgmi.connected_to_cpu) {
	if (!adev->gmc.xgmi.connected_to_cpu &&	!adev->gmc.is_app_apu) {
		if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
			dev_info(adev->dev, "MEM ECC is active.\n");
			adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
+19 −15
Original line number Diff line number Diff line
@@ -169,8 +169,19 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset)
{
	int ret = AMDGPU_RAS_SUCCESS;

	if (adev->gmc.xgmi.connected_to_cpu ||
		adev->gmc.is_app_apu) {
		if (reset) {
			/* MCA poison handler is only responsible for GPU reset,
			 * let MCA notifier do page retirement.
			 */
			kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
			amdgpu_ras_reset_gpu(adev);
		}
		return ret;
	}

	if (!amdgpu_sriov_vf(adev)) {
		if (!adev->gmc.xgmi.connected_to_cpu) {
		struct ras_err_data err_data = {0, 0, 0, NULL};
		struct ras_common_if head = {
			.block = AMDGPU_RAS_BLOCK__UMC,
@@ -183,13 +194,6 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset)
			obj->err_data.ue_count += err_data.ue_count;
			obj->err_data.ce_count += err_data.ce_count;
		}
		} else if (reset) {
			/* MCA poison handler is only responsible for GPU reset,
			 * let MCA notifier do page retirement.
			 */
			kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
			amdgpu_ras_reset_gpu(adev);
		}
	} else {
		if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
			adev->virt.ops->ras_poison_handler(adev);