Commit 38557c6f authored by Adam Skladowski's avatar Adam Skladowski Committed by Bjorn Andersson
Browse files

dt-bindings: clock: add QCOM SM6115 display clock bindings 



Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM6115 SoC.

Signed-off-by: default avatarAdam Skladowski <a39.skl@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
[bjorn: Minor fix of binding description]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com
parent 1a58ee13

Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml

0 → 100644
+70 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock Controller for SM6115



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description: |

  Qualcomm display clock control module which supports the clocks and

  power domains on SM6115.



  See also:

    include/dt-bindings/clock/qcom,sm6115-dispcc.h



properties:

  compatible:

    enum:

      - qcom,sm6115-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: Board sleep clock

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY0

      - description: GPLL0 DISP DIV clock from GCC



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmcc.h>

    #include <dt-bindings/clock/qcom,gcc-sm6115.h>

    clock-controller@5f00000 {

      compatible = "qcom,sm6115-dispcc";

      reg = <0x5f00000 0x20000>;

      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

               <&sleep_clk>,

               <&dsi0_phy 0>,

               <&dsi0_phy 1>,

               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

include/dt-bindings/clock/qcom,sm6115-dispcc.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2022, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H



/* DISP_CC clocks */

#define DISP_CC_PLL0			0

#define DISP_CC_PLL0_OUT_MAIN		1

#define DISP_CC_MDSS_AHB_CLK		2

#define DISP_CC_MDSS_AHB_CLK_SRC	3

#define DISP_CC_MDSS_BYTE0_CLK		4

#define DISP_CC_MDSS_BYTE0_CLK_SRC	5

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC	6

#define DISP_CC_MDSS_BYTE0_INTF_CLK	7

#define DISP_CC_MDSS_ESC0_CLK		8

#define DISP_CC_MDSS_ESC0_CLK_SRC	9

#define DISP_CC_MDSS_MDP_CLK		10

#define DISP_CC_MDSS_MDP_CLK_SRC	11

#define DISP_CC_MDSS_MDP_LUT_CLK	12

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK	13

#define DISP_CC_MDSS_PCLK0_CLK		14

#define DISP_CC_MDSS_PCLK0_CLK_SRC	15

#define DISP_CC_MDSS_ROT_CLK		16

#define DISP_CC_MDSS_ROT_CLK_SRC	17

#define DISP_CC_MDSS_VSYNC_CLK		18

#define DISP_CC_MDSS_VSYNC_CLK_SRC	19

#define DISP_CC_SLEEP_CLK		20

#define DISP_CC_SLEEP_CLK_SRC		21



/* DISP_CC GDSCR */

#define MDSS_GDSC			0



#endif