Commit 3886edbb authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.6-rockchip-dts32-1' of... 

Merge tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and
additional operating points for rk3288-tinker.

* tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger
  ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger
  ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker
  ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron

Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@phil


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents afa7f6eb a950c4c6

arch/arm/boot/dts/rk3288-tinker.dtsi

+12 −1
Original line number Diff line number Diff line
@@ -113,6 +113,17 @@ &cpu0 { 
	cpu0-supply = <&vdd_cpu>;

};



&cpu_opp_table {

	opp-1704000000 {

		opp-hz = /bits/ 64 <1704000000>;

		opp-microvolt = <1350000>;

	};

	opp-1800000000 {

		opp-hz = /bits/ 64 <1800000000>;

		opp-microvolt = <1400000>;

	};

};



&gmac {

	assigned-clocks = <&cru SCLK_MAC>;

	assigned-clock-parents = <&ext_gmac>;
@@ -175,7 +186,7 @@ vdd_cpu: DCDC_REG1 { 
				regulator-always-on;

				regulator-boot-on;

				regulator-min-microvolt = <750000>;

				regulator-max-microvolt = <1350000>;

				regulator-max-microvolt = <1400000>;

				regulator-name = "vdd_arm";

				regulator-ramp-delay = <6000>;

				regulator-state-mem {

arch/arm/boot/dts/rk3288-veyron-brain.dts

+9 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


/dts-v1/;

#include "rk3288-veyron.dtsi"

#include "rk3288-veyron-broadcom-bluetooth.dtsi"



/ {

	model = "Google Brain";
@@ -40,6 +41,14 @@ vcc5_host2: vcc5-host2-regulator { 
};



&pinctrl {

	pinctrl-names = "default";

	pinctrl-0 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff

	>;



	hdmi {

		vcc50_hdmi_en: vcc50-hdmi-en {

			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;

arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi

0 → 100644
+22 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth

 * chip.

 *

 * Copyright 2019 Google, Inc

 */



&uart0 {

	bluetooth {

		pinctrl-names = "default";

		pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,

			    <&bt_dev_wake>;



		compatible = "brcm,bcm43540-bt";

		host-wakeup-gpios	= <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;

		shutdown-gpios		= <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;

		device-wakeup-gpios	= <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;

		max-speed		= <3000000>;

		brcm,bt-pcm-int-params	= [01 02 00 01 01];

	};

};

arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi

+0 −21
Original line number Diff line number Diff line
@@ -136,27 +136,6 @@ trackpad@15 { 
};



&pinctrl {

	pinctrl-0 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Wake only */

		&suspend_l_wake

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Sleep only */

		&suspend_l_sleep

		&bt_dev_wake_sleep

	>;



	buttons {

		ap_lid_int_l: ap-lid-int-l {

			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;

arch/arm/boot/dts/rk3288-veyron-fievel.dts

+10 −4
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ / { 
		     "google,veyron-fievel-rev0", "google,veyron-fievel",

		     "google,veyron", "rockchip,rk3288";



	/delete-node/ bt-activity;



	vccsys: vccsys {

		compatible = "regulator-fixed";

		regulator-name = "vccsys";
@@ -215,7 +213,11 @@ &gpio0 { 
			  "PHY_PMEB",



			  "PHY_INT",

			  "REC_MODE_L",

			  /*

			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call

			   * it REC_MODE_L.

			   */

			  "RECOVERY_SW_L",

			  "OTP_OUT",

			  "",

			  "USB_OTG_POWER_EN",
@@ -382,7 +384,11 @@ &gpio7 { 
			  "PWR_LED1",

			  "TPM_INT_H",

			  "SPK_ON",

			  "FW_WP_AP",

			  /*

			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call

			   * it FW_WP_AP.

			   */

			  "AP_FLASH_WP_L",

			  "",



			  "CPU_NMI",