Commit 3999edf8 authored by Meera Patel's avatar Meera Patel Committed by Alex Deucher
Browse files

drm/amd/display: Initialize necessary uninitialized variables 



This commit initializes uninitialized variables.
For some compilers uninitialized variable warnings are treated as Error.

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Acked-by: default avatarAlan Liu <haoping.liu@amd.com>
Signed-off-by: default avatarMeera Patel <meera.patel@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6c3162d0

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 


	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

		int dpp_inst, dppclk_khz, prev_dppclk_khz;

		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;



		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

+5 −5
Original line number Diff line number Diff line
@@ -4090,9 +4090,9 @@ static bool commit_minimal_transition_state(struct dc *dc, 
		struct dc_state *transition_base_context)

{

	struct dc_state *transition_context = dc_create_state(dc);

	enum pipe_split_policy tmp_mpc_policy;

	bool temp_dynamic_odm_policy;

	bool temp_subvp_policy;

	enum pipe_split_policy tmp_mpc_policy = 0;

	bool temp_dynamic_odm_policy = 0;

	bool temp_subvp_policy = 0;

	enum dc_status ret = DC_ERROR_UNEXPECTED;

	unsigned int i, j;

	unsigned int pipe_in_use = 0;
@@ -4372,8 +4372,8 @@ bool dc_update_planes_and_stream(struct dc *dc, 
	 * cause underflow. Apply stream configuration with minimal pipe

	 * split first to avoid unsupported transitions for active pipes.

	 */

	bool force_minimal_pipe_splitting;

	bool is_plane_addition;

	bool force_minimal_pipe_splitting = 0;

	bool is_plane_addition = 0;



	populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);

	force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(

drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1659,7 +1659,7 @@ static int dcn315_populate_dml_pipes_from_context( 
{

	int i, pipe_cnt, crb_idx, crb_pipes;

	struct resource_context *res_ctx = &context->res_ctx;

	struct pipe_ctx *pipe;

	struct pipe_ctx *pipe = NULL;

	const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;

	int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;

	bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1892,7 +1892,7 @@ int dcn32_populate_dml_pipes_from_context( 
{

	int i, pipe_cnt;

	struct resource_context *res_ctx = &context->res_ctx;

	struct pipe_ctx *pipe;

	struct pipe_ctx *pipe = NULL;

	bool subvp_in_use = false;

	struct dc_crtc_timing *timing;

	bool vsr_odm_support = false;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

+1 −1
Original line number Diff line number Diff line
@@ -3194,7 +3194,7 @@ static void CalculateFlipSchedule( 
	unsigned int HostVMDynamicLevels;

	double TimeForFetchingMetaPTEImmediateFlip;

	double TimeForFetchingRowInVBlankImmediateFlip;

	double ImmediateFlipBW;

	double ImmediateFlipBW = 1.0;

	double HostVMInefficiencyFactor;

	double VRatioClamped;