Loading arch/mips/pci/pci-octeon.c +5 −10 Original line number Diff line number Diff line Loading @@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } /* Enable the PCIe normal error reporting */ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); if (pos) { /* Update Device Control */ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); } pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); Loading Loading
arch/mips/pci/pci-octeon.c +5 −10 Original line number Diff line number Diff line Loading @@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } /* Enable the PCIe normal error reporting */ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); if (pos) { /* Update Device Control */ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); } pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); /* Find the Advanced Error Reporting capability */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); Loading